Responsibilities
THE ROLE
AMD is seeking an experienced Tile Place & Route (PnR) Lead to lead the physical implementation and execution of complex SoC designs at advanced process nodes. This role combines deep technical expertise in physical design with leadership responsibilities across multiple programs, engineers, and cross-functional teams.
As a Tile PnR Lead, you will be responsible for driving implementation strategy, execution planning, design quality, schedule adherence, and technical mentorship. You will work closely with Architecture, RTL Design, Timing, CAD, Methodology, Physical Verification, and Full Chip teams to deliver world-class products.
THE PERSON
The ideal candidate is a recognized technical leader with a proven track record of delivering high-quality silicon across multiple successful tape-outs. You are equally comfortable solving challenging technical problems, mentoring engineers, driving execution across global teams, and influencing methodology direction.
You possess strong communication skills and can effectively engage customers, project leadership, methodology teams, and senior management while maintaining focus on execution excellence.
KEY RESPONSIBILITIES
Technical Leadership
- Lead physical implementation of complex SoC tiles from floorplan through tapeout.
- Drive overall Tile PnR strategy including floorplanning, placement, CTS, routing, timing closure, congestion management, IR/EM closure, and signoff readiness.
- Define implementation methodologies and best practices to improve PPA, scalability, and design quality.
- Drive technical decisions impacting schedule, product quality, and silicon success.
- Lead root-cause analysis and resolution of complex implementation challenges.
Program Execution
- Own execution planning, milestones, risk management, and quality metrics for critical IPs and SoC tiles.
- Coordinate activities across Design, Timing, CAD, Methodology, Full Chip Floorplan, Power, and Verification teams.
- Drive closure on schedule-critical and tapeout-critical issues.
- Provide regular status updates to technical and management leadership.
Team Leadership & Mentorship
- Mentor and develop Tile PnR engineers across multiple experience levels.
- Conduct technical reviews and provide implementation guidance.
- Lead training and knowledge-sharing initiatives across the organization.
Innovation
- Drive adoption of new implementation methodologies, automation, and AI-enabled design solutions.
- Influence future physical design flows and tool direction.
- Partner with CAD teams to improve productivity, scalability, and design predictability.
PREFERRED QUALIFICATIONS
- BS/MS in Electrical Engineering, Computer Engineering, or related field.
- Industry experience in physical design.
- Demonstrated technical leadership across multiple projects or product families.
- Multiple successful tape-outs at advanced technology nodes.
- Proven experience leading critical tiles or IPs.
- Recognized expert in Tile PnR and physical implementation.
- Experience leading globally distributed engineering teams.
- Expertise in congestion analysis, timing architecture, power optimization, and PPA improvement.
- Experience with AI-assisted implementation methodologies.
- Familiarity with ICC2, Fusion Compiler, PrimeTime, RedHawk/Totem, Calibre, and related implementation flows.
Location
#LI-JE1
Qualifications
Benefits offered are described: AMD benefits at a glance.
