Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with physical design from RTL to GDSII, including synthesis, floor planning, place and route, and timing closure.
- Experience with scripting languages in one or more of the following: Perl, Python, or Tcl.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in floor planning, block integration, static timing analysis, sign-off.
- Experience executing low-power physical design implementation using industry-standard EDA tools (Innovus/FC).
- Experience in sign-off convergence including STA, electrical checks, and physical verification.
- Experience in utilizing AI techniques for faster and optimal Physical Design Convergence (e.g., timing, floorplanning, power grid, and clock tree design).
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Physical Design Engineer, you will collaborate closely with cross-functional design, Design for Testing (DFT), architecture, power, and packaging engineers. In this role, you will address complex physical implementation issues at advanced process nodes, utilizing micro-architectural insights and practical logic circuit solutions. You will evaluate and optimize design options to deliver Performance, Power, and Area (PPA) for the next generation of Tensor Processing Unit (TPU) blocks and sub-chips.
The US base salary range for this full-time position is $138,000-$198,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities- Perform physical design of complex blocks from Register-Transfer Level (RTL) to Graphic Data System (GDS).
- Use problem-solving, debugging skills and collaborate cross-functional teams to achieve the best Power/Performance Analysis (PPA).
- Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized implementation and sign-off domains.
- Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design trade-offs for physical design closure.
