Physical Design Engineer

Etched

• $130K — $160K *
Enterprise Technology
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • 5-10+ years of experience in physical design (PD)
  • Proficient in design methodology from RTL synthesis to GDSII sign-off
  • Experience with timing closure on 5nm process nodes and below
  • Familiarity with EDA tools like Cadence and Synopsys for RTL-to-GDSII flows
  • Knowledge of sign-off tools such as PrimeTime and Voltus
  • Understanding of low power design methodologies and associated tools
  • Creative thinker with a deep grasp of first principles in PD.

Responsibilities

  • Own block-level implementation and verification
  • Run physical design (PD) flows to achieve block closure
  • Collaborate with RTL designers for PPA improvements
  • Drive project dashboards related to physical design convergence
  • Optimize tool flows with EDA vendors for feature incorporation
  • Supervise 3rd party design work for physical design
  • Improve CAD infrastructure and automate PD flows.

Benefits

  • Medical, dental, and vision benefits with generous coverage
  • $500 monthly credit for waiving medical benefits
  • $2,000 monthly housing subsidy for local employees
  • Relocation assistance for moves to San Jose
  • Wellness benefits covering fitness and mental health
  • Complimentary daily lunch and dinner in the office.
Full Job Description
Job Summary

Etched is looking for exceptional Physical Design engineers to join our team. In this role, you
will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed.

Key Responsibilities
  • Deeply understand what is involved in physical design
  • Running PD flows to close blocks, support ASIC infrastructure, automate PD flows,
    improve CAD infrastructure
  • Collaborate with RTL Designers and provide Physical Design feedback to improve PPA
  • Drive dashboards that show the convergence of projects related to PD
  • Optimize tool flows, working with EDA vendors to incorporate the latest features
  • Accountable for block level closure
  • Supervise the outsourcing of physical design to a 3rd party service


You may be a good fit if you have
  • 5-10+ years of previous experience with PD
  • Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
  • Experience with back-end design and timing closure on advanced process nodes (5nm
    and below)
  • Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler)
    automated RTL-to-GDSII flows
  • Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
  • Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS,
    routing, IR drop, and EM/antenna analysis
  • Deeply creative and able to think from first principles


Strong candidates may also have experience with
  • Familiarity with modern ML and LLM model architectures
  • Ability to program with Python or another scripting language
  • Familiarity with AI tools for programming/coding
  • Startup experience or comfort working in fast-paced environments


Benefits
  • Medical, dental, and vision packages with generous premium coverage
    • $500 per month credit for waiving medical benefits
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch + dinner in our office
  • Unlimited compute budget subject to ROI justification


This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.

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