Job Summary
We are seeking a Physical Design Engineer with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes. The role will focus on synthesis, PPA optimization, floorplanning, timing closure, and collaboration with RTL, architecture, physical design, and external implementation teams.

Key Responsibilities
• Perform synthesis using Cadence Genus for large, timing-challenged designs.
• Drive PPA (power, performance, area) optimization through synthesis and early implementation stages.
• Develop and refine floorplans using Cadence Innovus.
• Collaborate closely with RTL teams to provide timely feedback on design quality, constraints, and architectural tradeoffs.
• Partner with external P&R teams to iterate toward timing closure and PPA optimization.
• Identify and address timing bottlenecks early in the flow to improve convergence.

Required Qualifications
• At least 5 years of physical design experience.
• Hands-on experience with Cadence Genus and Innovus.
• Strong understanding of timing closure and correlation between synthesis and implementation.
• Hands-on experience with advanced or cutting-edge technology nodes, such as N5, N3, or below.
• Ability to work cross-functionally with RTL, architecture, physical design, and external implementation teams.

Preferred Qualifications
• Proven experience with large-scale SoC or AI-class designs.