Job Details:

Job Description:

About the Role

Altera is seeking a PhD-level Engineer/Physical AI Architect to help define the next generation of Physical AI platforms for robotics, industrial automation, machine vision, and autonomous systems. The candidate will drive system architecture and workload analysis across heterogeneous compute platforms combining CPUs, DSPs, FPGA fabric, AI accelerators, GPUs, memory subsystems, and high-speed sensor interfaces. The role will focus on mapping real-world Physical AI workloads to optimized hardware/software architectures and influencing future Altera product roadmaps.

As part of Altera's Embedded Architecture team, you will work across CPU, GPU, Real-Time Unit (RTU), Video, and Physical AI technologies, helping shape the future of heterogeneous computing platforms. You will join a core architecture group at the forefront of innovation, driving technology strategy and influencing next-generation silicon, software, and platform roadmaps. This role provides a unique opportunity to analyze and optimize complex AI, vision, perception, planning, and control workloads across heterogeneous compute engines including CPUs, DSPs, FPGA fabric, GPUs, and AI accelerators, while helping define the architecture of future intelligent systems and programmable computing platforms.

This role will help shape Altera's Physical AI strategy and future programmable computing platforms!

Key Responsibilities

• Define sensor-to-actuator Physical AI reference architectures.
• Analyze and partition AI, vision, perception, planning, and control workloads across CPU, DSP, FPGA fabric, GPU, and AI accelerators.
• Drive architecture tradeoffs involving performance, latency, power, memory bandwidth, and determinism.
• Develop workload models, benchmarks, and performance projections for robotics and autonomous systems.
• Collaborate with customers, ecosystem partners, and internal silicon teams to identify future platform requirements.
• Influence next-generation Altera SoC, FPGA, memory, interconnect, and accelerator roadmaps.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$133,200 - $190,000 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

Qualifications:

Minimum Qualifications:

• PhD in Electrical Engineering, Computer Engineering, Computer Science, Robotics, or related field.
• 1+ years of experience and research interest in system architecture, embedded computing, AI acceleration, robotics, or heterogeneous computing.
• 1+ years understanding of CPU, DSP, FPGA, GPU, AI accelerator, memory, and interconnect architectures.
• Experience with AI/ML, computer vision, robotics, or autonomous systems workloads.
• Proven track record of technical leadership, innovation, and architecture definition.

Preferred Qualifications:

• Experience with ROS2, edge AI, machine vision, autonomous systems, or industrial robotics.
• Knowledge of FPGA-based acceleration and heterogeneous computing platforms.
• Publications, patents, or recognized contributions in AI, robotics, or computer architecture.

Job Type:
Regular

Shift:
Shift 1 (United States of America)

Primary Location:
San Jose, California, United States

Additional Locations: