Job SummaryWe are seeking a highly skilled Silicon Validation Engineer to own PCIe bringup and qualification on our silicon. As the technical owner of PCIe validation, you will drive electrical characterization, link training debug, protocol-level validation, and end-to-end performance validation - working closely with design, DV, SI/PI, Firmware, and Platform teams. You will be hands-on in the lab and equally comfortable tracing issues from link margin optimization all the way through protocol debug and performance tuning.
Key Responsibilities- PCIe Bringup & Link Debug
- Own PCIe validation strategy, test plan, and execution across silicon revisions
- Bring up PCIe links on new silicon: link up / link training optimization, LTSSM debug, lane margining, equalization tuning
- Debug LTSSM state transitions, link training failures, recovery events, and correctable/uncorrectable errors
- Work with SI/PI on channel and package co-design feedback for future silicon
- Electrical Characterization
- Characterize PCIe TX/RX against the PCIe base spec and channel spec across PVT and across lanes
- Perform electrical validation: eye diagram, jitter, preset sweeps, TX FFE / RX CTLE+DFE tuning, compliance pattern testing
- Operate lab equipment including high-bandwidth real-time and sampling scopes, BERT, VNA, protocol analyzers, and pattern generators
- Protocol Validation
- Validate PCIe protocol behavior: TLPs, DLLPs, ordered sets, flow control, credit management, and ordering rules
- Debug and root-cause issues spanning electrical, protocol, firmware, and system layers; drive them to closure with the right owner
- Performance Validation
- Run end-to-end performance validation: throughput, latency, DMA performance, multi-lane scaling, error injection and recovery
- Infrastructure & Automation
- Build and improve validation infrastructure: automation, regression, and coverage reporting
- Partner with design, DV, firmware, and platform teams to ensure robust coverage across silicon revisions
You may be a good fit if you have (Must-have qualifications)- BS/MS in Electrical Engineering, Computer Engineering, or equivalent; 5+ years of PCIe silicon validation experience
- PCIe Electrical
- PCIe base spec and channel spec - Gen3/Gen4/Gen5 required; Gen6 a plus
- TX and RX equalization: FFE, CTLE, DFE, preset behavior, and EQ link training
- LTSSM, link training and status state machines, recovery and error handling
- Link bringup and link optimization methodology
- Hands-on with lab equipment: high-bandwidth scopes, BERT, VNA, protocol analyzers, pattern generators
- PCIe Protocol
- TLP and DLLP structure, types, and handling
- PCIe ordered sets (TS1/TS2, SKP, EIEOS, etc.)
- DMA, flow control, credits, ordering, and error reporting
- Config space and enumeration
Strong candidates may also have experience with (Nice-to-have qualifications)Experience with any of the following is beneficial but not required.
- End-to-end PCIe performance validation: throughput / latency / QoS characterization against a root complex or endpoint
- Ability to write and modify firmware and/or software test cases - C, Python, or driver-level Linux - to exercise PCIe from the host or device side
- Cross-layer debug experience: signal integrity to protocol analyzer to firmware trace
- Experience with PCIe compliance testing and PCI-SIG workshops
- Familiarity with a variety of PHY and controller IPs
- Scripting and automation experience: Python, test frameworks, lab automation
Benefits- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Housing subsidy of $2k per month for those living within walking distance of the office
- Relocation support for those moving to San Jose (Santana Row)
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch and dinner in our office
We are a fully in-person team in San Jose and Taipei, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
