We are seeking a highly experienced Design Engineer to enable our APTD team in the Bonding & Packaging Design space. In this role you will drive the electrical, thermal, and thermo-mechanical design and characterization of next-generation semiconductor packages, including High Bandwidth Memory (HBM), wafer-to-wafer (W2W), Chip-on-Wafer (COW), Flip Chip, and Through-Silicon-Via (TSV) technologies. You will work closely with global multidisciplinary teams to turn complex simulation results into practical design guidelines and future technology roadmaps. A key focus of the role is leveraging AI and machine learning tools, including generative AI and predictive analytics to improve learning, accelerate simulations, and enable data-driven decision making within Advanced Packaging R&D. Job Responsibilities • Maintain deep subject-matter knowledge of semiconductor and advanced electronics packaging technologies such as HBM, W2W, COW, Flip Chip, and TSV • Drive design advancements through a detailed understanding of electrical parasitics, insertion loss, and impedance mismatches of various interconnects as a function of materials, geometries, temperature, and humidity, capturing the corresponding multiphysics mechanisms in simulation • Propose short and long-term solutions to improve thermals and kick off projects aligned to thermal improvement roadmaps. • Apply understanding of Chip-Package Interactions (CPI) in 2.5D, 3D systems, and internal qual packages; drive sensitivity studies and data collection to validate mechanical and thermo-mechanical stress/strain structural models; Propose design rules with clear justification and explanation for partnering teams. • Work with internal/external vendors and testing labs to design and implement effective testing procedures to characterize material dielectric constants and decay values for simulation analysis. • Integrate AI workflows into package design and package technology evaluations and creation; Drive AI-enabled technology development for advanced packaging and heterogeneous integration. Minimum Qualifications • MS or Ph.D. in Electrical Engineering, Material Science, Applied Physics, or a related field • 15-20 years of professional experience in a relevant engineering area with at least 10 years of direct experience in electrical, thermal, and mechanical package analysis, modeling, and validation of electronic packages in the semiconductor industry or equivalent. • Solid understanding of design and process impacts on thermal performance, including the contribution of each layer to total thermal impedance • Proficiency with engineering tools for Design of Experiments (DOE) and statistical analysis (e.g., JMP or equivalent) • Demonstrated ability to integrate AI/ML and generative AI tools into engineering workflows, technical assessments, and daily productivity Preferred Qualifications • Experience in Signal Integrity analysis and high-speed package designs, defining characterization (CHAR) plans, and defining DOEs needed to develop package solutions for specific problems • Familiarity with Cadence layout tools to open and review designs of test vehicles or new memory concepts • Data acquisition experience and numerical analysis proficiency in MATLAB, Excel, JMP, etc. As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.