Job Description

About the Treo Platform
The Treo Platform is a high-performance analog and mixed-signal platform built on 65nm Bipolar-CMOS-DMOS (BCD) technology. Supporting voltages from 1-90V and operating temperatures up to 1756C, Treo enables scalable SoC solutions for automotive, medical, industrial, and AI data-center applications. Its modular analog IP is integrated into digital-on-top architectures manufactured in onsemi's 300mm East Fishkill, NY fab.
About the Role
We are seeking a Mixed-Signal Verification Engineer III to verify analog and mixed-signal IP integrated into digital-on-top SoC environments on the Treo platform. This mid-level individual contributor role reports directly to the Analog Design Team Manager. You will own the development and execution of mixed-signal verification solutions, leveraging SystemVerilog and behavioral modeling to ensure power and clock IP meet functional and integration requirements prior to tape-out.

Responsibilities

Key Responsibilities
 Own mixed-signal verification for assigned analog IP blocks using SystemVerilog and UVM-based methodologies.
 Develop scalable digital-on-top testbenches incorporating behavioral models of analog IP such as PLLs, LDOs, DC/DC converters, and oscillators.
 Translate analog specifications into executable verification plans, assertions, coverage, and checkers.
 Develop and maintain behavioral models using SystemVerilog real-number modeling to abstract analog behavior for system-level simulation.
 Execute regressions, analyze results, and drive debug to root cause across analog, digital, and mixed-signal boundaries.
 Verify configuration, calibration, monitoring, and fault-handling interfaces between analog IP and digital logic.
 Coordinate with analog designers, digital verification, and system teams to ensure verification completeness and sign-off readiness.
Behavioral Modeling & Abstraction
 Create and refine behavioral and functional models suitable for large-scale SoC simulation while preserving key performance characteristics.
 Define modeling assumptions, limitations, and validation strategies in collaboration with analog designers.
 Contribute to abstraction and co-simulation strategies balancing accuracy, runtime, and reuse.
Tools, Flows & Quality
 Use industry-standard digital, mixed-signal, and AMS simulation tools.
 Apply coverage-driven verification practices and participate in verification reviews.
 Follow established version control, regression, and documentation practices; propose incremental flow improvements.
Collaboration & Technical Leadership
 Operate with moderate independence while mentoring junior verification engineers.
 Provide technical input during IP definition and integration reviews from a verification perspective.
 Proactively identify verification risks and communicate them clearly to stakeholders.

Qualifications

Minimum Qualifications
 Bachelor's or Master's degree in Electrical Engineering or related field.
 Minimum of 6 years of experience in mixed-signal or digital IC verification.
 Strong proficiency in SystemVerilog and UVM-based verification.
 Hands-on experience building behavioral models using Verilog-A/AMS or SystemVerilog real-number modeling.
 Experience verifying analog IP within digital-on-top SoC environments.
Preferred Qualifications
 Familiarity with power management or clocking architectures (BGs, PLLs, LDOs, DC/DCs).
 Experience with coverage-driven verification and assertion-based methodologies.
 Exposure to automotive or industrial silicon reliability and safety requirements.
 Interest in automation, scripting, or AI-assisted verification workflows.
Success Metrics
 High-quality, reusable mixed-signal verification environments delivered on schedule.
 Early and effective identification of functional and integration issues in analog IP.
 Reduced verification escapes at SoC and silicon bring-up stages.
 Demonstrated technical growth and mentoring contribution within the verification team.

About the Team

We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.