Job Details:Job Description:Join Intel as a Mixed Signal Design Verification Engineer and play a crucial role in shaping the future of cutting-edge technology. In this role, you will be at the forefront of ensuring Intel's mixed signal logic components meet the highest standards of functionality, performance, and reliability.
As part of a world-class team, your work will directly contribute to the design of advanced architectures and technologies that will power tomorrow's innovations.
Responsibilities will include but are not limited to:- Develop and execute comprehensive verification plans for mixed signal logic components to ensure alignment with microarchitecture specifications.
- Design and implement test benches and verification environments using advanced methodologies such as OVM and UVM.
- Perform system-level simulation to verify functionality, analyze power and timing, and identify potential design issues.
- Collaborate with digital and analog architects, RTL developers, and physical design teams to optimize verification strategies and meet performance, power, and functional goals.
- Debug presilicon issues by replicating, root causing, and implementing corrective measures for failing tests.
- Create and maintain analog behavioral models and contribute to the development of reusable verification infrastructure and methodologies.
- Document test plans, verification results, and drive technical reviews with design and architecture teams.
The ideal candidate should show the following behavioral traits:- Exceptional problem-solving skills, willing to debug complex presilicon issues.
- Strong collaboration and communication skills, with a track record of working effectively with cross-functional teams.
- Passion for innovation and a commitment to excellence in engineering.
Qualifications:Minimum qualifications are required to be initially considered for this position.
- A Bachelor's or BS degree and/or equivalent knowledge in a specialized field, with at least 3 years of relevant experience,
- OR A Master's degree and/or equivalent knowledge in a specialized field, with at least 2 years of relevant experience,
- OR PhD and/or equivalent knowledge in a specialized field, with at least 1 year of relevant experience,
Experience listed above should be a combination of the following:- Verification methodologies such as OVM and UVM.
- System Verilog and Verilog for test environment and design verification.
- Developing test environments for functional verification of mixed signal logic components.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Experience with power intent design and/or UPF (Unified Power Format) modeling.
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location:US, California, Folsom
Additional Locations:US, California, Santa Clara, US, Colorado, Fort Collins, US, Oregon, Hillsboro
Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 07/14/2026
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
