Qualifications

• 4+ years of experience in silicon design with ASICs and SOCs.
• Proficiency in SystemVerilog, Python, C/C++, or similar coding languages.
• Demonstrated capability in silicon micro-architecture for CPUs, GPUs, or accelerators.
• Hands-on skills with design synthesis and related quality flows.
• Experience collaborating with verification teams for performance assessments.
• Knowledge of high-speed I/O IP is advantageous.
• Background in data manipulation logic, such as caches and buffers, is beneficial.

Responsibilities

• Contribute to scalable silicon design methodologies across various design levels.
• Lead and manage complete subsystem and chip-level design deliverables.
• Coordinate sign-off reviews for architecture and design progress.
• Collaborate closely with verification, DFT, and physical design teams.
• Optimize performance, power, and area results during design phases.

Benefits

• Subsidized health, dental, vision, and life insurance with HSA contributions.
• 4 weeks of paid time off plus 12 company holidays and 3 weeks flex work.
• 12 weeks of paid parental leave for all paths to parenthood.
• Annual support of $1,500 for professional development and learning.
• 401K with a 5% company match, promoting financial well-being.
• Team lunches, quarterly off-sites, and regular town halls for connection.
• Rideshare cost coverage for commutes, ensuring productive travel.
• $50 monthly perks allowance for personalized benefits.
• Remote work support with home-tech setup and wifi expense reimbursement.