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X In most instances, this position requires in-person interviews as part of the hiring process.
Minimum qualifications: - Bachelor's degree in Electrical Engineering (EE), Computer Science (CS), Computer Engineering, or equivalent practical experience.
- 15 years of industry experience in memory controller architecture, micro-architecture, or ASIC design.
- Experience in architecture, micro-architecture, and design of DRAM memory controllers.
- Experience in ASIC architecture performance analysis, performance tools, and simulator development at different abstraction levels (e.g., cycle-accurate, TLM, or functional).
Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Deep domain knowledge in coherent interconnects, caches, fabrics, memory systems, and memory controllers.
- Understanding of hardware performance monitors, profiling, power management, and optimization.
About the jobAs the Mempath Architect, you will shape the future of our DRAM memory sub-system and controller architecture for consumer SoCs. Your role brings together the architectural responsibilities for both memory sub-system and memory controller under a single roof, as these two subsystems are tightly coupled and heavily influence each other, your role offers a unique end-to-end view to drive architectural alignment, performance optimization, and hardware-software co-design.
You will collaborate with hardware designers, validation teams, and software architects to build and test exceptional technologies. You will be at the forefront of memory system innovation, leveraging cutting-edge developments in DDR, process-in-memory, and other emerging DRAM advancements.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $240000 - $333000 (USD) 25% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Define and maintain the end-to-end architectural strategy across memory sub-systems and memory controllers for consumer SoCs.
- Lead performance, power, and area trade-off analyses, feature design, clocking, and power state management across memory IPs.
- Author comprehensive hardware architectural specifications, system-level design requirements, and programmer guides for next-generation memory controllers.
- Evaluate architectural choices by developing C-models, executing workload simulations, and collaborating with verification and emulation teams.
- Serve as the primary technical contact for memory path latency, power optimization, and performance across cross-functional engineering teams.
