General Summary:Job DescriptionWe are looking for an experienced
Memory Subsystem Performance Architect to lead HBM performance modeling, analysis, and optimization of high-bandwidth memory subsystems for next-generation SoCs. This role drives architecture exploration from early concept through post-silicon, partnering closely with architecture, design, and software teams.
Responsibilities- Develop and maintain C++ / SystemC performance models for HBM-based memory subsystems.
- Define and execute experiments to evaluate HBM architecture features, memory controller behavior, and system-level trade-offs.
- Identify performance bottlenecks across HBM, interconnect, caches, and compute, and propose architecture improvements.
- Collaborate with cross-functional teams (SoC, NoC, memory controller, power, software) to influence design decisions.
- Research and track industry trends and innovations in HBM, 3D-stacked memory, and advanced packaging.
- Support post-silicon performance characterization, correlation, and model refinement.
Minimum Qualifications- 3+ years of experience in performance modeling, memory architecture, or system architecture.
- Strong C++ proficiency; experience with SystemC/TLM modeling.
- Solid understanding of memory hierarchies and DRAM systems.
Preferred Qualifications- Hands-on experience with HBM2/HBM2E/HBM3 architectures.
- Experience with AI/ML, GPU, or HPC-class SoCs.
- Familiarity with post-silicon performance analysis and silicon correlation.
- Ability to translate performance data into clear architectural recommendations.
KeywordsHBM, Performance Modeling, SystemC, C++, Memory Architecture, SoC Architecture, AI/ML, Post-Silicon
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Pay range and Other Compensation & Benefits: $140,000.00 - $210,000.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
