Cadence Design Systems

Memory Interface PHY IP, Design Engineering Architect

Cadence Design Systems$136K — $253K *
Telecommunications & Hardware
11 - 15 years of experience
Job Overview by Ladders

Qualifications

  • M.S. degree in Electrical Engineering, Computer Engineering, or related field
  • Minimum 15 years of industry experience in memory interface PHY, high-speed IO, or related domains
  • Strong background in memory interface PHYs, JEDEC standards, and protocols
  • Proven ability to own customer-facing technical engagements and drive issues to closure
  • Excellent written and verbal communication skills

Responsibilities

  • Contribute to PHY architecture development with understanding of memory interface PHY IPs
  • Drive architecture decisions aligned with JEDEC standards and protocols
  • Understand PHY/IO circuit architecture, including TX/RX, and power delivery
  • Act as customer-facing technical architect during pre-sales and post-delivery support
  • Collaborate with Sales, Marketing, and Program teams on customer engagements
  • Provide expert-level IP support, including architecture clarification
  • Work with design, verification, and silicon validation teams to ensure architectural intent

Benefits

  • Paid vacation and paid holidays
  • 401(k) plan with employer match
  • Employee stock purchase plan
  • Variety of medical, dental and vision plan options
Full Job Description
A Design Engineering Architect provides the technical leadership needed to translate evolving standards and customer requirements into scalable, high-quality IP architectures. This role reduces execution risk, accelerates customer engagements, and strengthens long-term product competitiveness.

Design Engineering Architect - Roles & Responsibilities
  • Contribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g., DDR, LPDDR), including electrical, timing, power, and protocol considerations
  • Drive architecture decisions aligned with JEDEC standards, protocols, and compliance requirements
  • Good understanding of PHY/IO circuit architecture including TX/RX, clocking, termination, power delivery, and signal integrity trade-offs
  • Act as a customer-facing technical architect during pre-sales, evaluations, and post-delivery support, clearly articulating architecture choices and trade-offs
  • Collaborate closely with Sales, Marketing, and Program teams to support customer engagements, RFIs, and technical proposals
  • Provide expert-level IP support to customers, including architecture clarification, feature customization
  • Work cross-functionally with design, verification, layout, and silicon validation teams to ensure architectural intent is correctly implemented
  • Review and guide architecture specifications, design reviews, and technical documentation
  • Influence product and technology roadmap planning by identifying future standards, protocol evolution, and customer-driven requirements
  • Demonstrate strong communication, accountability, and technical ownership across internal and external interactions


Required Qualifications
  • M.S. degree in Electrical Engineering, Computer Engineering, or related field
  • Minimum 15 years of industry experience in memory interface PHY, high-speed IO, or related domains
  • Strong background in memory interface PHYs, JEDEC standards, and protocols
  • Proven ability to own customer-facing technical engagements and drive issues to closure
  • Excellent written and verbal communication skills

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

About Cadence Design Systems

Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Learn more about Cadence Design Systems
Size
9,300 employees
Market Cap
$43.9 billion
Industry
Net Income
$590.6 million
Founded
2018
5 Year Trend
+10.5%
Revenue
$2.6 billion
NASDAQ

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