Job Details:Job Description: You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies. In this position your responsibilities will include, but may not be limited to:
Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
Memory bit-cell and complex periphery IC layout and automation.
Memory array/IP design, memory circuit innovation, test-chip design.
Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.
The Advanced Design (AD) team is part of Intel’s larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel’s internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel’s advanced CMOS process technologies.
Qualifications:Minimum Qualifications:
Master’s degree in Electrical Engineering, Computer Engineering, Electrical & Computer Engineering, or a related discipline, including 4 years of professional experience gained through either internships or full-time employment
Ph.D. in one of the same fields listed above.
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM
Design trade-offs between power, performance, and area (PPA)
Custom digital circuit design, simulation, layout design, and verification
Experience in EDA tools used for custom digital and memory circuit design.
Preferred Qualifications:
Ph.D. with 1-2 years of professional experience gained through either internships or full-time employment.
Design technology co-optimization (DTCO)
Post-Si validation experience.
Knowledge of the CMOS ASIC design flow.
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location: US, Oregon, Hillsboro
Additional Locations:
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location: US, Oregon, Hillsboro
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
