About the RoleWe are seeking a Member of Technical Staff, Senior Formal Verification Engineer.
In this role, you will be responsible for developing and executing formal verification strategies and techniques to ensure design correctness. You will collaborate closely with Architects, RTL Design and Verification Engineers to understand the requirements, develop formal verification infrastructure and drive closure on the critical design blocks. You will be part of an early-stage startup working on an exciting product in the Artificial Intelligence/DataCenter space. The work involves learning advanced LLM in modern data centers and applications to design memory acceleration.
The ideal candidate possesses strong expertise in formal verification methodologies, SystemVerilog assertions (SVA), RTL design concepts and industry standard formal verification tools.
This role will be performed onsite from one of our offices in Santa Clara, CA or Boston, MA.
Essential Duties & Responsibilities- Analyze architecture and design specifications to identify the formal verification requirements.
- Develop and execute formal verification plans for Netpreme silicon, IP and subsystems.
- Build formal verification environments, SystemVerilog Assertions (SVA), formal properties including assumptions, constraints, abstractions and checkers.
- Perform property checking, model checking, equivalence checking, deadlock and livelock analysis.
- Debug formal verification failures, analyze counter examples and work with design team to resolve issues.
- Drive verification closure through formal coverage analysis and proof convergence.
- Contribute to verification methodology improvements and formal verification best practices.
- Mentor junior verification engineers and provide technical leadership within the team.
- Participate in design reviews, architecture discussions, verification reviews and sign-off activities.
- Collaborate with Simulation, Emulation and validation teams to ensure comprehensive verification coverage.
- Guide the team by using formal techniques in optimizing the design to meet aggressive performance, power and area goals.
Qualifications- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum of 10+ years of experience in ASIC/SOC verification with at least 7+ years of formal verification experience.
- Strong understanding of digital design fundamentals, computer architecture.
- Experience with Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, or equivalent formal verification tools.
- Outstanding technical expertise in formal verification methodologies and tools, strong hands-on experience in SystemVerilog Assertions (SVA), formal properties.
- Experience verifying complex control logic, datapath designs, protocol interfaces.
- Strong debugging and root-cause analysis skills.
- Excellent leadership, communication and stakeholder management skills.
- Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
- Proficiency in scripting languages such as Tcl, Python, Perl or Shell.
Preferred Qualifications- Knowledge of UVM and simulation based verification methodologies.
- Experience with CDC, RDC, low power verification and equivalence checking.
- Familiarity with GPU, high performance computing and Memory based architectures.
- Prior technical leadership or mentoring experience.
Compensation & Benefits- Competitive salary commensurate with experience including base salary, performance-based bonus, and early stage equity grant
- Comprehensive benefits including health, dental, vision, and life insurance
- Well-equipped, sunny offices in Santa Clara, CA and Boston, MA
- Relocation assistance and visa sponsorship
- Perks include a daily lunch stipend, 401k match, and more
- A collaborative, continuous-learning work environment with smart, dedicated colleagues engaged in developing the next generation of architecture for high-performance computing
