Manager/Director of Hardware Engineering

Baya Systems

$140K — $180K *
Telecommunications & Hardware
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 8+ years of ASIC/IP development experience, with 2-3 years in leadership or management.
  • Strong background in high-speed protocols such as PCIe, CXL, and Ethernet.
  • Proficiency in SystemVerilog, Verilog, and EDA simulation/synthesis flows.
  • Deep understanding of UVM/OVM verification methodologies and coverage analysis.
  • Proven problem-solver with a startup mindset in a dynamic environment.

Responsibilities

  • Lead and mentor a team of 8-12 RTL and DV engineers.
  • Oversee the development of high-speed interconnect IP from specifications to tape-out.
  • Ensure robust, coverage-driven verification processes are in place.
  • Collaborate with architecture, physical design, and system teams to meet PPA and timing requirements.
  • Establish engineering metrics and agile project management tools for on-time delivery.

Benefits

  • Comprehensive medical, dental, and vision benefits.
  • 401(k) retirement plan.
  • Equity in the company.
Full Job Description
Manager/Director of Hardware Engineering Santa Clara, CA (Onsite only) Reports to: VP of Hardware Engineering Role Overview As a Hardware Engineering Manager, you will lead a talented, first-level team of RTL Microarchitects and Design Verification (DV) Engineers. Operating in a fast-paced IP interconnect startup environment, you will own the end-to-end execution of high-speed interconnect IP blocks. You will ensure first-pass silicon success by driving microarchitecture, RTL design, and rigorous verification methodologies. What You'll Do • Team Leadership: Directly manage, mentor, and grow a team of 8-12 RTL and DV engineers. • Execution & Delivery: Drive the development of high-speed interconnect IP from microarchitecture specifications to RTL implementation and tape-out. • Verification Excellence: Oversee the development of robust, coverage-driven verification test plans, UVM/OVM environments, and emulation platforms. • Cross-Functional Collaboration: Work closely with architecture, physical design, and system teams to balance power, performance, area (PPA), and timing requirements. • Process Optimization: Define and establish engineering metrics, standard methodologies, and agile project management tools to meet strict tape-out milestones. Requirements & Qualifications • Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field. • Experience: 8+ years of industry experience in ASIC/IP development, with at least 2-3 years in a technical leadership or management role. • Technical Domain: Strong background in high-speed protocols (e.g., PCIe, UCIe, CXL, Ethernet, or advanced SerDes). • Design Skills: Proficiency in SystemVerilog, Verilog, and industry-standard EDA simulation/synthesis flows. • Verification Skills: Deep understanding of modern verification methodologies (UVM/OVM), constrained random testing, formal verification, and coverage analysis. • Startup Mindset: Highly adaptable, proactive problem-solver with a proven track record of delivering results in a dynamic, fast-moving environment. Compensation: • Salary commensurate with experience • Performance incentives • Comprehensive medical, dental, and vision benefits • 401(k) retirement plan • Equity

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