Qualifications

• Bachelor's Degree plus 9 years or Graduate Degree plus 7 years of experience; candidates with 13 years of experience in lieu of a degree will be considered.
• Strong understanding of FPGA design processes and experience in designing verification strategies.
• Ability to obtain U.S. government clearance is mandatory.
• Familiarity with complex design test scoping and coverage metrics is essential.
• Experience with hardware verification languages, especially System Verilog, is preferred.

Responsibilities

• Execute and contribute to the FPGA verification plan to ensure design integrity.
• Architect UVM test cases for various FPGA blocks to validate functionality.
• Develop reusable testbench modules and environments for efficient testing processes.
• Define functional coverage models aligned with design-under-test requirements for comprehensive validation.
• Utilize UVM to build drivers, monitors, and scoreboards tailored to specific DUT needs.
• Work autonomously or with minimal supervision to create effective test bench solutions.
• Focus on identifying design issues and enhancing design robustness through innovative approaches.

Benefits

• 9/80 work schedule allowing for every other Friday off.
• Opportunity to work in a dynamic, fast-paced environment.
• Involvement in cutting-edge FPGA technologies and architectures.