Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in one or more of the following areas: computer architecture, embedded firmware, ASIC design or verification, integration and enablement of first or third-party IPs.
- Experience in hardware/software integration including developing and debugging firmware.
- Experience with RTL development design or design verification (DV).
- Experience leading a cross-functional team of digital systems.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 5 years of experience with C /Python software design principles.
- Experience developing firmware for embedded systems or accelerators.
- Experience as a tech lead integrating hardware/software systems in accelerators.
- Proficiency in debugging firmware using simulation tools or working knowledge of RTOS internals.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will be working on ASIC development, validation, software, tools, and methodologies and will have the ability to push the boundaries of chip-development and hardware/software integration and validation. You will own cross-functional work streams focussed on end-to-end HW/SW integration and validation to demonstrate HW, SW, and system functionality and performance. You will help the chip team accomplish key silicon development criteria, meet chip and system schedules and achieve readiness for production in various silicon and system validation environments. You will serve as a key bridge between specification, design, and verification teams as well as compiler and performance teams with technical depth and breadth across the ML compute IP. As a lead, you will own strategy, planning, validating, and delivering hardware and software systems which are shown to be functional and performant. You will be responsible for coordination, debug, and enablement of the platform.
The US base salary range for this full-time position is $192,000-$278,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities - Lead hardware, software, and system integration for custom silicon, bridging architecture, design, and compiler teams to ensure platform delivery.
- Own functional and performance validation requirements, ensuring successful demonstration across tape-out and post-silicon phases.
- Drive ML compute feature bring-up by integrating first and third-party IPs and developing hardware-validating firmware.
- Execute HW-SW co-simulation strategies utilizing RTL simulation, emulation, and FPGA environments to streamline silicon validation.
- Design microbenchmarks and detailed validation plans based on cross-functional design specifications to verify IP functionality and performance.
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