Job Summary:

The PsiQuantum Foundry Engineering team develops and supports a silicon photonics technology platform in collaboration with our development partners. This work includes enabling new materials, process modules, and technology capabilities required to support PsiQuantum's product development roadmap for a commercially useful quantum computer.

The Layout Verification / Parasitic Extraction Engineer will support the physical and electrical verification of photonic integrated circuits within PsiQuantum's silicon photonics technology platform. This role will focus on validating the electrical routing associated with photonic circuits, including routing for photonic devices, bias lines, heaters, phase shifters, modulators, monitor structures, control signals, and electrical I/O interfaces.

This is a hands-on execution role suited for a detail-oriented engineer who is comfortable working with EDA tools. The engineer will run established DRC, LVS, ERC, antenna, density, and parasitic extraction flows; review verification reports; generate extracted outputs; and work with layout and design engineers to identify and resolve layout verification issues prior to tapeout.

Responsibilities:

• Run established DRC, LVS, ERC, antenna, density, and parasitic extraction flows using existing scripts, runsets, and foundry PDK decks.
• Validate electrical routing in photonic integrated circuit layouts, including routing for photonic devices, bias lines, heaters, phase shifters, modulators, monitor structures, control signals, and electrical I/O interfaces.
• Generate extracted netlists and extracted views for post-layout electrical simulation.
• Maintain organized logs, reports, run directories, and status trackers.
• Support block-level and chip-level verification activities prior to tapeout.

Experience/Qualifications:

Required qualifications:

• Bachelor's degree in Electrical Engineering, Physics, Microelectronics, or related field, or equivalent experience.
• Basic knowledge of IC layout and physical verification concepts.
• Exposure to DRC, LVS, or parasitic extraction.
• Familiarity with Linux or Unix environments.
• Strong attention to detail and ability to follow established procedures.
• Good communication and documentation skills.
• Demonstrated interest in quantum computing.
• Ability to contribute in a fast-moving start-up environment.

Preferred qualifications:

• Exposure to analog/mixed-signal ICs, or custom IC layout.
• Experience with Cadence Virtuoso, Siemens Calibre, Cadence Pegasus/PVS, Cadence Quantus, and similar EDA tools.
• Familiarity with post-layout simulation flows and extracted netlists.
• Basic scripting experience in Python.
• Exposure to silicon photonics, photonic integrated circuits, or optoelectronics.
• Demonstrated interest in quantum computing, silicon photonics, or advanced semiconductor technology.

The ranges below reflect the target ranges for a new hire base salary. One is for the Bay Area (within 50 miles of HQ, Palo Alto), the second one (if applicable) is for elsewhere in the US (beyond 50 miles of HQ, Palo Alto). If there is only one range, it is for the specific location of where the position will be located. Actual compensation may vary outside of these ranges and is dependent on various factors including but not limited to a candidate's qualifications including relevant education and training, competencies, experience, geographic location, and business needs. Base pay is only one part of the total compensation package. Full time roles are eligible for equity and benefits. Base pay is subject to change and may be modified in the future.

U.S. Base Pay Range

$110,000-$150,000 USD

Bay Area Pay Range

$150,000-$170,000 USD