The DRAM Design Engineering Group (DDEG) develops advanced memory solutions by tightly integrating design, layout, process integration, and CAD expertise. The team focuses on delivering high-quality, manufacturable DRAM designs while continuously improving layout methods, automation, and documentation to support scalable and predictable execution.
The Layout Engineer translates schematics and related geometry into manufacturable semiconductor layouts that meet design intent, process rules, and schedule commitments for advanced DRAM products. This role partners closely with Design, Process Integration, and CAD teams to floorplan, implement, verify, and deliver custom digital, memory, and analog layouts while contributing to methodology and automation improvements.
Responsibilities- Develop multi-dimensional layouts and detailed drawings for semiconductor devices from schematics and related geometry using CAD tools, from floorplan through final design.
- Perform layout verification including DRC, LVS, dimensional checks, and quality reviews; verify completed drawings, artwork, and digitized plots.
- Write and maintain specifications and documentation; prototype, codify, and share layout methods, automation, and SOPs to improve efficiency and quality.
- Coordinate with global partners to deliver block-level layouts on schedule, supporting tapeout and mask generation while maintaining quality standards.
- Lead layout planning for assigned blocks or sub-projects, provide technical guidance, mentor engineers, and ensure alignment to priorities and schedules.
Minimum Qualifications- Bachelor's degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field.
- Familiarity with layout tools and methodologies, including Cadence Virtuoso VXL and Calibre for DRC/LVS and verification.
- Exposure to semiconductor custom, memory, or analog layout and experience producing detailed drawings from schematics and geometry.
- Solid understanding of CMOS processes, design rules, and layout-dependent effects.
- Demonstrated problem-solving ability in ambiguous situations with strong attention to detail and quality.
Preferred Qualifications- Three or more years of semiconductor custom, memory, or analog layout experience with block or project leadership, mentoring, and schedule management.
- DRAM, LPDDR, or HBM memory product layout experience.
- Scripting experience using SKILL and/or Python and experience building layout methodology or automation.
- Strong collaboration skills across global, multi-functional teams and strong written documentation abilities.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
