JB061568 - Lead ASIC DFT Engineer

USM

• $120K — $160K *
San Jose, CA 95123In-Person
Enterprise Technology
Less than 5 years of experience
Today
Be an Early Applicant
Job Overview by Ladders

Qualifications

  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, and test techniques.
  • Deep expertise in scan architecture, ATPG, MBIST, JTAG, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion and ATPG setup and simulation.
  • Experience with MBIST implementation, verification, and SMS preferred.
  • Strong understanding of PLLs, RTL design, and physical design implementation.

Responsibilities

  • Lead ASIC DFT initiatives with full ownership from start to finish.
  • Apply DFT methodologies to enhance test coverage and functionality.
  • Perform debug analysis and validation on silicon designs.
  • Utilize EDA tools to execute scan architecture and ATPG setups.
  • Oversee successful implementation and verification of MBIST.
  • Conduct simulations and fault coverage analysis to ensure design integrity.
  • Collaborate across teams to address multi-domain integration challenges.

Benefits

  • Comprehensive health and wellness programs.
  • Flexible work arrangements to support work-life balance.
  • Opportunities for professional development and training on advanced tools and techniques.
  • Supportive team environment that encourages innovation and collaboration.
Full Job Description
  • Start Date: Interview Types
  • Skills ASIC DFT, Visa Types Green Card, US Citiz..


    • Required Skills & Qualifications

    • Strong hands-on experience in ASIC DFT with end-to-end ownership.
    • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
    • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
    • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
    • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
    • Experience with MBIST implementation and verification; SMS experience preferred.
    • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
    • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
    • Proven post-silicon debug and silicon bring-up experience.
    • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
    • Strong communication skills and the ability to work independently with minimal ramp-up.


    Preferred Experience

    • MBIST post-silicon validation.
    • ATPG simulations and fault coverage debug.
    • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
    • DFT SDC creation and DFT timing closure support.
    • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
    • TCL/PERL scripting for DFT automation, reporting, and debug.
    • Experience working across multiple ASIC technology nodes and complex product development cycles.
    • Familiarity with yield learning, diagnosis, and manufacturing test optimization.
    * Ladders Estimates

    Similar Jobs

    Ad banner background

    Get Ready For Your
    Next Interview

    More Jobs at USM

    More Enterprise Technology Jobs

    Find similar JB061568 - Lead ASIC DFT Engineer jobs:

    NationwideSan Jose, CA