Qualifications

• 5-7 years of hands-on experience in ASIC DFT with full project accountability.
• Strong knowledge of DFT principles, fault models, and associated testing techniques and coverage.
• Expertise in scan architectures and various debugging methodologies including JTAG and boundary scan.
• Proficient in using EDA tools from Synopsys, Cadence, and Siemens/Mentor for ASIC design and verification.
• Demonstrated success with scan insertion processes and debug activities in ATPG setups.
• Experience in implementing and validating MBIST, with preferred knowledge of SMS.
• Worked with complex SoC designs and integration in multi-domain environments.

Responsibilities

• Lead ASIC DFT initiatives from conception through to implementation and debugging.
• Develop and execute extensive DFT test strategies encompassing scan, MBIST, and boundary scan methodologies.
• Collaborate with cross-functional teams to optimize DFT designs and validate functionality throughout the product lifecycle.
• Perform detailed analysis on scan architectures and debug fault coverage during the testing phase.
• Utilize EDA tools to facilitate test generation, simulation, and design rule checks (DRC).
• Drive post-silicon debug processes and contribute to successful silicon bring-up activities.
• Implement DFT solutions that enhance yield learning and manufacturing test optimization.

Benefits

• Opportunities for continuous learning and professional development.
• Possibility of working with cutting-edge ASIC technology and products.
• Collaborative work environment with a focus on innovation.
• Exposure to diverse and challenging projects in the semiconductor field.