Job Details:
Job Description:
The Role and Impact
As an IP Logic Design Engineer, you will play a pivotal role in driving next-generation semiconductor innovation. In this role, you will develop and optimize cutting-edge IP logic designs, contributing directly to Intel's mission to shape the future of computing. Your work will impact Intel's success by delivering high-quality IP blocks and subsystems for seamless integration into full-chip designs, enabling superior power, performance, and efficiency in Intel's products. Collaborating alongside a team of world-class engineers, you will have the opportunity to influence design architecture, tackle meaningful challenges, and shape the future of semiconductor technology.
Key Responsibilities:
- Develop logic design and register transfer level (RTL) coding for IP blocks using languages such as System Verilog and Verilog.
- Optimize logic designs to meet power, performance, area, and timing goals.
- Participate in defining architecture and microarchitecture features for IP blocks.
- Collaborate with cross-functional teams to review verification plans, ensuring comprehensive validation of design features.
- Identify and resolve failures in RTL tests, implementing corrective measures to ensure design correctness.
- Apply power-saving techniques such as clock gating and power gating to enhance energy efficiency.
- Support System-on-Chip (SoC) customers with the integration and verification of IP blocks, ensuring high-quality handoff and smooth execution.
- Use industry-standard tools and methodologies to ensure design integrity and compliance with quality assurance standards.
Qualifications:
Minimum Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
- 0 to 1 or more years of experience with a Bachelor's degree, or 0 years of experience with a Master's degree.
- Proficiency in RTL design and development using System Verilog and Verilog.
- Hands-on experience with clock design, clock gating, and clock domain crossing.
- Experience with UPF low-power coding and debugging techniques.
- Familiarity with problem-solving approaches for power, performance, area, and timing optimization.
Preferred Qualifications:
- Master's degree in Electrical Engineering, Computer Engineering, or related field.
- Understanding of microarchitecture design principles and strategies.
- Strong technical collaboration skills to work effectively in a team environment.
- Demonstrated ability to adapt to evolving technologies and industry trends.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Folsom
Additional Locations:
US, California, Santa Clara
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $105,650.00-172,860.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
