Minimum qualifications:- Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience.
- 1 year of experience in DFT architecture, implementation, Automatic Test Pattern Generation (ATPG), and verification for SoCs.
Preferred qualifications:- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Design-for-Test (DFT) Engineer, you will define, implement, and deploy design-for-test methodologies, including Scan, Memory Built-In Self-Test (MBIST), Joint Test Action Group (JTAG), and iJTAG, for digital or mixed-signal chips or Intellectual Properties (IPs). You will define DFT architecture and create DFT flows for test chips and next-generation System on Chips (SoCs) in partnership with the Design and Physical Design teams. You will also verify test logic, generate test patterns, and debug test coverage issues.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $116000 - $166000 (USD) 15% bonus target equity benefits
Responsibilities- Complete Test Design Rule Checks (TDRC) and design changes to fix violations to achieve test quality.
- Drive design and integration of DFT logic in Test Chips including IEEE1149.1 TAP controller, Boundary Scan, scan chains, MBIST, Clock Control block, and other DFT IP blocks.
- Insert and connect MBIST logic, including test collars around memories, MBIST controllers, and electronic fuse (eFuse) logic, to core and Test Access Port (TAP) interfaces.
- Design Verification of DFT logic and test pattern generation.
- Develop DFT timing constraints in Synopsys Design Constraints (SDC) for DFT logic.
