HPE Labs - Principal AI and Machine Learning Research Engineer
This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office.
Job Description:The Emerging Accelerators Team within HPE Labs has an immediate opening for a Principal AI/ML Engineer. HPE Labs is an international research organization with its headquarters and largest facility located in Milpitas, California. As the central research organization for Hewlett Packard Enterprise (HPE), HPE Labs' purpose is to deliver breakthrough technologies and technology advancements that provide a competitive advantage for the company, by investing in fundamental science and technology in areas of interest to HPE and getting the resulting technologies ready for adoption into new and existing markets.
We expect all our researchers to provide thought leadership and technical influence both internally and externally to HPE, as well as take innovative ideas and make them real - contributing along the full range from initial novel ideas to design, development, implementation, evaluation, and technology transfer. The ideal candidate can thrive in an applied research environment, balancing significant technical and scientific contributions with the ability to bring such contributions to practice through innovative solutions that address the needs of our customers and partners. We expect the successful candidate to collaborate with HPE Labs research teams as well as with external partners, and to work in alignment with HPE's broader innovation community. Excellent software systems building skills are a significant plus
Role and Responsibilities- Synthesize research directions and vision based on technology insight and tracking advances across academia and industry. Define, lead, and delegate research activities while also contributing directly to research results.
- Research, conceive, develop, and model new architectures for AI/ML accelerator integrated circuits (IC) via simulators or system coding/analysis. Research, conceive, develop, and evaluate algorithms for AI/ML workloads on accelerator ICs or hardware, particularly in the Analog In-Memory Computing architecture space, potentially utilizing hardware/software co-design techniques. Research, conceive, develop, and evaluate compiler and mapping operations for optimal assignment of computational workloads to accelerator hardware.
- As a member of a project team in a leadership role, conceive, architect, design, and test integrated circuit IP for AI/ML research test chips. Conceive, architect, and design test and system boards and software for IC characterization and application demonstration.
- Provide technical guidance and mentorship for junior researchers, interns, and postdocs. Collaborate with internal and external technology partners.
- Author and provide guidance on conference presentations and journal papers reporting on new research results. Drive technical innovation leading to invention disclosures and patent filings.
Qualifications and Education Requirements- PhD degree in Electrical Engineering, Computer Science, Data Science, or equivalent.
- 5+ years of experience in AI & Machine learning ( academic or industrial).
- Must have strong experience in analog in-memory computing research, computing in memory, or processing in memory.
- Work experience with resistive RAM (ReRAM or RRAM) as a non-volatile memory device
- Strong experience leading research projects.
- For candidates with only a Master degree, they must hold 10+ years experience in AI & ML research.
Preferred Skills- Experience with in-memory computing accelerators.
- Experience with micro architecture design for custom accelerators.
- Experience in deep learning research, algorithms, and data structures.
- Experience in design and test of integrated circuit IP for AI/ML applications.
- Experience with emerging analog memory devices for computing applications such as RRAM, PCM, and others.
- Experience in system software, GPU acceleration, deep learning model execution and performance optimization.
- Experience working with FPGAs for emulation and system design.
- High level of creativity.
- Self-motivated and proactive, with strong leadership qualities.
- Ability to work with ambiguity.
- Ability to lead execution of complex projects.
- Demonstrated ability to generate, frame, and carry out leadership research as shown, for example, by papers published in top-tier conferences or journals.
Additional Skills:Artificial Intelligence Technologies, Cross Domain Knowledge, Data Engineering, Data Science, Design Thinking, Development Fundamentals, Full Stack Development, IT Performance, Machine Learning Operations, Scalability Testing, Security-First Mindset
What We Can Offer You:Health & WellbeingWe strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional DevelopmentWe also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have - whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional InclusionWe are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
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Job:Engineering
Job Level:TCP_05
"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
- United States of America: Annual Salary USD 160,000 - 303,000 in Colorado // 172,000 - 349,000 in California
The listed salary range reflects base salary. Variable incentives may also be offered."
Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html
The estimated job application period closure is June 8 2026; this timeline is provided for transparency and internal planning purposes.
