About the Position:In this role you will use SystemVerilog and UVM methodologies, working from specifications to deliver coverage-closed, verified, and debugged FPGA designs. You will be responsible for developing verification environments and leveraging 3rd party VIP as appropriate. You will verify FPGA-based designs, blocks, and sub-systems within complex systems, working closely with design teams. You will be part of a strong and experienced engineering team, contributing to high-performance FPGA development projects.
Key Responsibilities:- Perform design verification of FPGA-based systems integrating custom logic and 3rd-party IP blocks.
- Develop and maintain verification environments using SystemVerilog and UVM methodologies.
- Create and execute test plans, testbenches, and test cases.
- Debug simulation issues and identify root causes.
- Collaborate with design engineers to ensure high-quality deliverables.
- Perform code and functional coverage analysis and drive closure.
- Support hardware bring-up and validation activities when required.
Key Qualifications:- 5+ years of experience in FPGA or ASIC verification.
- Strong knowledge of Verilog / SystemVerilog and hardware design/verification concepts.
- Hands-on experience with UVM / OVM methodologies.
- Experience with simulation tools (e.g., Questa, VCS, Xcelium).
- Familiarity with constrained random verification, assertions, and functional coverage.
- Understanding of FPGA architectures and toolchains (e.g., Xilinx, Intel/Altera).
- Experience with standard bus protocols such as AXI, APB, or similar.
- Experience with high-speed interfaces and protocols (e.g., PCIe, Ethernet, DDR, JESD) is considered an asset.
- Scripting experience (Python, Perl, or similar) is an asset.
- Team player - excellent interpersonal and communication skills.
Compensation:$120,000 to $170,000 plus company bonus and benefits plan.
Salary is heavily dependent on individual experience and capability.
This is a new position. Only candidates selected for an interview will be contacted. Artificial Intelligence tools are not used in the evaluation and selection of candidates.
