FPGA Engineer

Sapsol Technologies Inc

• $110K — $130K *
Melbourne, FL 32935In-Person
Telecommunications & Hardware
5 - 7 years of experience
Today
Be an Early Applicant
Job Overview by Ladders

Qualifications

  • Expert-level verification engineer with strong SystemVerilog and/or UVM experience.
  • Experience in FPGA verification including lab testing and/or hardware FPGA design verification testing.
  • Familiarity with Xilinx products is a strong plus.
  • Ability to communicate effectively with engineers, particularly at the India GETC-I site.
  • Proven ability to provide technical guidance on DO-254 processes.

Responsibilities

  • Develop RTL code and testbenches using VHDL, Verilog, and SystemVerilog.
  • Create UVM constrained random environments for verification.
  • Conduct static timing, linting, and clock-domain-crossing (CDC) analyses.
  • Manage requirements capture and decomposition for projects.
  • Oversee architecture development, synthesis, and placement & routing.

Benefits

  • Opportunity to work with a leading technology company.
  • Potential for career growth through collaboration with emerging engineers.
  • Engagement in challenging and innovative projects.
  • Exposure to cutting-edge technologies in hardware verification.
Full Job Description
Required Skills:
  • Expert-level verification engineer with strong SystemVerilog and/ or UVM experience or
  • FPGA verification in lab testing and/or Hardware FPGA design verification testing
  • Experience with design on Xilinx products would be a strong plus
  • expected to communicate effectively with emerging engineers at the India GETC-I site and provide both technical and process (DO-254) guidance to the verification team.


Core Responsibilities
  • RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog.
  • Verification: Create UVM constrained random environments and conduct static timing, linting, and clock-domain-crossing (CDC) analyses.
  • Hardware Lifecycle: Handle requirements capture, decomposition, architecture development, synthesis, and placement & routing. [1]

Key Qualifications
  • Experience: Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior designation).
  • Education: Degree in a STEM (Science, Technology, Engineering, Mathematics) field.
* Ladders Estimates

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