Parallel Partners

FPGA Engineer

Parallel Partners$80K — $100K *
Aerospace & Defense
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • 5+ years of FPGA design experience.
  • 2+ years of working with ASICs and/or FPGAs, including internships and research.
  • Proficient in SystemVerilog, Verilog, or VHDL RTL design for 2+ years.
  • Familiar with scripting and programming languages such as MATLAB, Python, C/C++, etc.
  • Experience in formal Software Development Lifecycle process.
  • Hands-on experience with firmware architecture and design.

Responsibilities

  • Participate in all phases of FPGA design flow from concept to production.
  • Develop high-level design requirements and block-level micro-architectures.
  • Create and optimize RTL designs focusing on DSP and digital communication blocks.
  • Develop test benches for verification and validate designs using MATLAB models.
  • Integrate SoC and FPGA designs, ensuring functionality emulation.
  • Perform design checks with EDA tools to ensure compliance and efficiency.
  • Collaborate with software engineers to create production software for FPGA designs.

Benefits

  • Medical insurance coverage.
  • Retirement plan options.
  • Paid Time Off (PTO) availability.
Full Job Description
FPGA Engineer, Linthicum Heights, MD

We are looking for multiple FPGA Engineer candidates at multiple levels for this position. Candidates must be US Citizens and cannot have Dual Citizenships. All candidates must be fully vaccinated with an FDA authorized and/or approved COVID-19 vaccine as a condition of employment. Requests for reasonable accommodations for medical, religious, or other reasons will be considered in accordance with applicable law. These positions are 100% Onsite.

Responsibilities:

- Participate in all phases of FPGA design flow, from concept to mass production.
- Develop high-level design requirements and block-level micro-architectures, partition design within ASIC/FPGA, create specification documents.
- Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer, error correction, etc.).
- Optimize designs for area, speed, and power to meet system requirements; analyze architectural trade-offs.
- Develop test benches and test cases for block-level functional verification, emphasizing bit-matching and self-checking.
- Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers.
- Participate in SoC and FPGA integration activities.
- Prototype designs on FPGA, focusing on closely emulating the final product functionality.
- Perform lint checking, CDC checking, logic equivalence checking, and other EDA tool-based checks.
- Work with backend/implementation teams to address synthesis, timing, layout, and DFT issues for ASICs.
- Bring-up and validate ASICs and FPGAs in the lab, utilize various lab equipment.
- Collaborate with software engineers in developing production software for your designs.

Qualifications:

- 5+ years of experience FPGA design.
- 2+ years of experience in working with ASICs and/or FPGAs (internship and research experience qualifies).
- 2+ years of experience in SystemVerilog, Verilog, or VHDL RTL design.
- 2+ years of experience in scripting and programming languages in two or more of the following: MATLAB, Python, C/C++, Tcl, Makefiles, Bash.
- Development experience in HDL (Verilog or VHDL).
- Experience developing software using a formal Software Development Lifecycle process (SDLC).
- Firmware architecture and design experience.

Minimum Qualifications:

- 2+ years of experience in designing DSP or digital communication system datapath blocks (e.g., filters, transforms, PHY blocks, loops, FEC, etc.).
- Experience in Xilinx advanced FPGAs, eval boards, and knowledge of FPGA design flow.
- Knowledge of different digital modulation techniques (e.g., PSK, QAM, OFDMA, etc.).
- Knowledge of wireless communications systems and standards (e.g., LTE, Wi-Fi, Bluetooth, etc.).
- Knowledge of industry standard interfaces, protocols, and architectures, PCIe, Ethernet, AMBA, DDR, etc.
- Experience in developing automated, self-checking test benches.
- Knowledge or understanding of UVM verification framework.
- Experience in EDA tools such as simulators (e.g., Questa), lint checkers (e.g., Spyglass), synthesis (e.g., Synopsys Synplify), FPGA tools (e.g., Vivado).
- Experience in synthesis and static timing analysis, knowledge of timing closure techniques for high-speed designs.
- Experience in ASIC/FPGA/SoC system-level/top-level integration.
- Familiarity with design for testability (DFT) and high reliability ASIC design and implementations.

Benefits include medical insurance, retirement plan, PTO, etc. Salary: 80K+ DOE. Keywords: Linthicum Heights MD Jobs, FPGA Engineer, FPGA, DSP, Xilinx, PSK, QAM, OFDMA, PCIe, Ethernet, AMBA, DDR, UVM, Questa, Spyglass, Synopsys, Synplify, Vivado, ASIC, Electrical Engineer, Maryland Recruiters, Information Technology Jobs, IT Jobs, Maryland Recruiting

About Parallel Partners

Parallel Partners is an investment management firm that specializes in private equity and venture capital investments. The firm focuses on investing in early-stage companies in the technology, healthcare, and consumer sectors. Parallel Partners was founded in 2018 and is headquartered in New York, New York.
Learn more about Parallel Partners
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