THE OPPORTUNITY
Silvus is seeking a
Senior FPGA / RTL Design Engineer reporting to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products. In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R&D. These are exciting projects targeted to address challenging real-world communication needs.
The Senior FPGA / RTL Design Engineer position will be based at Silvus headquarters in the heart of vibrant
West Los Angeles,CA and is on a hybrid schedule; a minimum of 3 days onsite per week is expected. On-site days are Mondays, Wednesdays, and Thursdays.
The following is a list of at least some of the current essential job functions of the position. Management may assign or reassign duties and responsibilities at any time at its discretion.
ROLE AND RESPONSIBILITIES
- Digital design architecting for wireless communication projects.
- Fixed point design of signal processing blocks while working with systems engineers.
- RTL coding, simulation, and test bench development.
- FPGA synthesis and timing closure.
- Hardware verification and troubleshooting; familiarity with logic analyzers.
- Provide support to the RF and Software Engineering teams.
REQUIRED QUALIFICATIONS
- Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant fields.
- Minimum 6 years of demonstrated experience in FPGA design; 4 years of FPGA design experience with a Master's of Science degree; 2 years of FPGA design experience with a PhD degree.
- Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.
- Proven expertise working with multiple clock-domain, high-utilization FPGA designs.
- Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
- NOTE - Must be a U.S. Person (U.S. Citizen, or U.S. Permanent Resident) due to clients under U.S. federal contracts.
PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES
- Master of Science degree in Electrical Engineering (MSEE).
- Basic MATLAB skill.
- Experience with communication systems on FPGA or ASIC designs.
COMPENSATIONThe pay range is NOT a guarantee. It is based on market research and peer data, and will vary depending on the candidate's experience and qualifications.
CA Pay Range
$100,000-$140,000 USD
Consistent with Motorola Solutions values and applicable law, we provide the following information to promote pay transparency and equity. Pay within this range varies and depends on job-related knowledge, skills, and experience. The actual offer will be based on the individual candidate.
NOTE - As a US Federal Contractor, Silvus Technologies requires that ALL candidates being considered for employment for any position (regardless of level) MUST be a U.S. Person (permanent resident or citizen). Stricter U.S. Citizen ONLY requirements (needed for some Engineering or R&D roles) will be included in the Required Qualifications section of the posted position. This does NOT apply to international positions; only job postings for positions located in the US. 
