Fellow, Post-Silicon Validation Architecture (Server CPUs)THE TEAMOur Server Platform Solutions Engineering team is the ultimate gatekeeper for the quality of every server product we ship including functional, electrical, and security post-silicon validation responsibility. They work closely with design, product engineering, platform software, and hardware teams on optimized bring-up and execution strategies including ensuring functional correctness, electrical compliance/margins, and enabling customer use cases. The validation team engages from the beginning of any design project through post-launch.
During the technical feasibility and development phases, Validation Architects ensure a product has the right controllability and observability features for testing and debugging. Emulation engineers must work closely with the design verification team and ensure content is ready and well tested in emulation before first silicon arrives in the lab.
The team develops the necessary tools and silicon/software hooks (e.g., DFx) to generate content with randomization, efficient failure debug, and automation infrastructure enabling the most efficient and effective execution and fastest path to launch. They embrace approaches such as "at-scale validation clusters" to ensure required quality.
The validation team has the pre-silicon responsibility of reviewing design milestones and qualifying these milestones for tape-out readiness. This requires quality checklists prepared collaboratively with partner teams. With the insights and knowledge developed during the development phase, the validation team will lead the bring-up efforts of any silicon in the lab.
THE PERSONAt the Fellow level, the Server CPU Validation Architect has business and technical acumen along with experience engaging with global validation organizations including engineering managers, program managers and specialized technical experts. They should have in-depth understanding of our product architecture and its requirements to meet our customer needs in terms of quality, schedule, and features. They will understand server silicon validation methodologies with experience in post silicon program ownership and a track record role-modeling a "zero customer escape" mentality. Quick responsiveness to customer needs, ability to clearly and crisply communicate issues, and discipline/passion in continuous improvement is expected.
The role will involve high level visibility of the most senior leaders inside and outside of the company. Strong executive level communication (verbal and written) and sound decision making is of utmost importance.
THE ROLE- Drive the development of CPU validation strategy and test plan
- Validation coverage & content/framework developer - owner of test strategy and execution to consistently find hard to detect CPU/SoC architectural/design issues and manufacturing defects and greatly reduce the time to root cause and deploy necessary workarounds.
- Engage with technical leaders to identify and develop tools and methodologies for validating next-generation server CPU technologies including PCIE, CXL, coherent interconnects, etc.
- At-scale validation strategist - top technical leader directing the usage of our global server farms to maximize overall quality as measured by customer impactful issues.
- System level emulation architect - priority setter and key strategist for emulation & prototyping.
- Drive requirements and priorities for automation capabilities needed for effective and timely execution of platform validation plan leading to product launch.
- Forward thinker that drives improvement to development process, code architecture and fosters a spirit of innovation and continuous improvement throughout the team
- Master debugger - "go-to" person for the toughest debug challenges involving security, power management, coherency, PCIE, memory, interrupts, etc. crossing the HW/SW boundaries. Draws on experience to drive continuous improvement in automated debug analysis methodologies and on-chip capabilities.
- Use of AI tools and techniques to accelerate validation tools and environment development
EDUCATION AND EXPERIENCE- BSEE, MSEE preferred
- Understanding of modern x86 microprocessor architecture and Server platform architecture
- Experience developing validation methodologies and infrastructure
- Test plan and test development experience
- Participated in silicon bring-up and debug
- Debug skills at both SoC and system level
- Familiarity with programming and scripting languages (C/C++, Python, ...)
- Working knowledge of Server operating systems (Linux, Windows)
- Self-driven team player who can work with minimal guidance
- Able to network, build relationships and drive effective decision-making across multiple functions and levels within the organization
- Excellent verbal and written English communication skills
- Strong analytical skills.
LOCATIONAustin, TX
Santa Clara, CA
Folsom, CA
This role is not eligible for visa sponsorship.#LI-LM1
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
