DV - Staff Verification Engineer - Serdes

Eliyan

$100K — $130K *
Telecommunications & Hardware
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • BS degree plus 7 years of verification experience, including 4+ years focused on PHY or high-speed interfaces
  • In-depth verification expertise in SerDes, PCIePHY, TX/RX equalization, and CDR
  • Strong UVM/SystemVerilog skills for test environment and assertion coding
  • Experience in mixed signal IP verification and third-party VIP integration
  • Preferred: Over 10 years of verification technical leadership experience
  • Preferred: Familiarity with formal verification tools like Jasper Gold or vc-formal
  • Preferred: Proficiency in Python, Perl, or Tcl scripting for verification tasks

Responsibilities

  • Develop and implement verification plans for SerDes and other PHYs
  • Create and manage UVM/SystemVerilog verification environments
  • Write and debug test cases compliant with SystemVerilog/UVM
  • Maintain regression environments for ongoing verification processes
  • Collaborate with design teams to ensure high-quality output
  • Track progress and manage test plan items towards RTL freeze
  • Stay current with industry trends and standards
  • Integrate third-party VIPs and manage associated feature/bug requests
  • Mentor junior verification engineers as a technical lead
  • Conduct GLS simulations for functional verification and power assessments

Benefits

  • Fun working environment
  • Excellent employee benefits package
  • Collaborative work with cross-functional experts
  • Emphasis on mentorship and leadership opportunities
  • On-site working arrangement Monday to Friday
Full Job Description
In this role you will lead the verification of Serdes. You will be developing state-of-the-art testbenches and unit/chip level test cases for best-in-class PHYs. You will own verification of TX/RX equalization and CDR. This is a hands-on technical leadership role. You'll define PHY verification architecture, write UVM/SV testbenches, and make sure that designs are bug free. You will work with a cross-functional team of experts. We offer a fun work environment with excellent benefits. ONSITE M-F. Key Responsibilities: • Develop and execute verification plans for Serdes, other PHYs, DSP blocks, TX/RX equalization and CDR. • Create and maintain SystemVerilog/UVM-based verification environments • Write and debug SystemVerilog/UVM compliant test cases for block and chip level • Maintain regression environments • Collaborate with design team to ensure design quality • Develop, maintain, and track various test plan items and progress towards RTL freeze • Stay up to date with industry trends, emerging technologies and progress in standards' bodies • Integration of 3rd party VIPs and coordinate feature/bug tracking requests • As a technical leader, mentor junior verification engineers • GLS simulation for functional verification and power calculations Required Qualifications: • BS + 7 years of verification experience with 4+ years in PHY or high-speed interfaces • Deep verification expertise in SerDes/PCIePHY, TX/RX equalization, CDR • Strong expertise in UVM/SystemVerilog, test environment and assertion coding • Experience in verifying mixed signal IPs as well as integration of VIPs Preferred Qualifications: • 10+ years with demonstrated verification technical leadership • Experience with Formal verification with Jasper Gold or vc-formal • Experience with GLS simulations • Python/Perl/Tcl scripting for design verification • Proficiency in 3rd party tools for regression management and coverage analysis We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans.

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