DSP - FEC Design Engineer

Celero Communications, Inc.

$110K — $130K *
US-AnywhereRemote in Ottawa, ON
Telecommunications & Hardware
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Master's or Ph.D. in Electrical Engineering, Mathematics, Computer Engineering, or related field.
  • Strong background in coding theory and error correction algorithms.
  • Experience with soft-decision FEC schemes for communication systems.
  • Familiarity with LDPC, staircase codes, or product codes.
  • Programming skills in C/C++, Python, MATLAB, or similar languages.
  • Experience in modeling communication systems and evaluating performance metrics.
  • Familiarity with hardware implementation languages like Verilog or VHDL is a plus.

Responsibilities

  • Research and evaluate forward error correction schemes for high-speed optical communications.
  • Design soft-decision FEC algorithms for optical modem implementations.
  • Develop coding schemes and high-performance FEC architectures.
  • Model and simulate FEC performance and interaction with DSP blocks.
  • Analyze performance trade-offs including coding gain and implementation complexity.
  • Develop simulation models for algorithm verification.
  • Collaborate with cross-functional teams for hardware implementation.

Benefits

  • Collaborative work environment among interdisciplinary teams.
  • Opportunity to work on cutting-edge communication technologies.
  • Engagement in challenging projects that influence product delivery.
  • Potential for professional development and growth within the company.
Full Job Description
DSP - FEC Design Engineer

Locations: Ottawa, Ontario, Canada or Vancouver, British Columbia, Canada

Key Responsibilities
• Research, develop, and evaluate forward error correction (FEC) schemes for high-speed optical communication systems.
• Design and optimize soft-decision FEC algorithms suitable for high-throughput optical modem implementations.
• Develop and evaluate coding schemes such as LDPC, staircase codes, or related high-performance FEC architectures.
• Model and simulate FEC performance in optical communication systems, including interaction with DSP blocks and channel impairments.
• Analyze performance trade-offs including coding gain, latency, throughput, and implementation complexity.
• Develop floating-point and fixed-point simulation models for algorithm verification.
• Implement bit-accurate and cycle-accurate models supporting ASIC implementation.
• Collaborate closely with DSP, ASIC, firmware, and verification teams to ensure efficient hardware implementation.
• Document algorithm design and simulation results.

Preferred Qualifications
• Master's or Ph.D. degree in Electrical Engineering, Mathematics, Computer Engineering, or related field.
• Strong background in coding theory and error correction algorithms.
• Experience with FEC schemes for communication systems, particularly soft-decision FEC.
• Familiarity with LDPC, staircase codes, product codes, or related modern FEC techniques.
• Experience evaluating coding gain, BER performance, and decoder complexity.
• Programming experience in C/C++, Python, MATLAB, or similar languages.
• Experience in modeling communication systems.
• Familiarity with DSP algorithms for communication systems.
• Experience with version control systems, specifically GitHub.
• Familiarity with hardware implementation considerations and languages such as Verilog or VHDL is a plus.
• Team player with a mindset focused on the successful delivery of the first product.

Javier Leon
Talent Acquisition

[email protected]
www.celero.inc

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