The Design Manager - Smart Analog & Sensors will lead the architecture, design, and execution of complex mixed-signal SoCs, with primary focus on digital subsystem design, IP integration, and end-to-end SoC realization for sensing-driven applications.
This role emphasizes SoC creation, compute + control integration, and scalable IP-based development, enabling smart sensing platforms for automotive and industrial markets. The analog/sensor content is treated as a system integration component, while the core leadership spans digital architecture, RTL design, and SoC integration.
Role OverviewThe Design Manager - Smart Analog & Sensors will lead the
architecture, design, and execution of complex mixed-signal SoCs, with primary focus on
digital subsystem design, IP integration, and end-to-end SoC realization for sensing-driven applications.
This role emphasizes
SoC creation, compute + control integration, and scalable IP-based development, enabling smart sensing platforms for automotive and industrial markets. The analog/sensor content is treated as a
system integration component, while the core leadership spans
digital architecture, RTL design, and SoC integration.
Key Responsibilities1. SoC Architecture & Digital Design Leadership- Define and drive SoC architecture for Smart Sensor platforms:
- Compute subsystems (MCU / DSP / AI accelerators)
- Interconnects (NoC, bus fabrics)
- Memory subsystems and hierarchy
- Control, security, and safety islands
- Lead top-level SoC integration, partitioning functionality across digital, analog, and software domains
- Drive hardware/software co-design, aligning system architecture with firmware and application requirements
2. IP Strategy & Integration- Own development, selection, and integration of internal and 3rd-party IP, including:
- Processor cores (e.g., RISC-V / MCU-class cores)
- DSP / ML accelerators
- Peripherals and connectivity IP
- Define IP reuse strategy and platformization across multiple programs
- Ensure robust IP qualification, integration methodology, and interoperability verification
3. RTL Execution & Design Quality- Lead teams responsible for:
- RTL micro-architecture and implementation
- Subsystem integration and top-level assembly
- Drive design best practices:
- Lint, CDC, RDC, low-power intent (UPF)
- Synthesis and timing closure alignment with PD
- Ensure high-quality handoff to DV, DFT, and Physical Design teams
4. End-to-End SoC Program Execution- Own delivery from specification 12 RTL 12 integration 12 tapeout 12 silicon bring-up
- Partner closely with:
- Design Verification, DFT, PD, and product engineering
- System architecture and applications teams
- Drive closure on:
- Functional correctness and coverage
- PPA (power, performance, area)
- Silicon bring-up readiness and debug strategy
- Align execution with system-level modeling and requirements definition flows
5. Smart Sensor System Integration- Integrate analog/sensor subsystems (AFE, RF, data converters) into digital SoC framework
- Drive system-level tradeoffs:
- Data path partitioning (analog vs digital vs software)
- Latency, power, and accuracy optimization
- Ensure seamless interaction between sensor front-end, compute, and software stack
Expected Salary Range$166,500.00 - $290,000.00
The exact Salary will be determined based on qualifications, experience and location.
