Role description

DFT Engineer

Associate III - Semiconductor Product Validation

UST is searching for a DFT Engineer with strong understanding of scan design, ATPG, fault models (stuck-at, transition, path delay), and test compression techniques.

The opportunity:
• Define and implement DFT architecture including scan, MBIST, LBIST, and boundary scan for ASIC/SoC designs
• Develop and integrate scan chains, compression techniques, and test points to achieve high fault coverage
• Perform ATPG pattern generation, simulation, and debug to meet coverage and quality goals
• Work closely with design, physical design, and verification teams to ensure DFT readiness across all design stages
• Execute DFT checks such as DRC, LVS, and timing closure in coordination with backend teams
• Debug silicon bring-up issues related to test failures and yield improvement
• Analyze test coverage reports and implement strategies to improve fault coverage and reduce test time
• Support manufacturing test, including tester bring-up, pattern validation, and failure analysis
• Develop and maintain DFT documentation, test plans, and sign-off reports.

This position description identifies the responsibilities and tasks typically associated with the performance of the position. Other relevant essential functions may be required.

What you need:
• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field
• 5+ years of experience in DFT for ASIC/SoC development
• Hands-on experience with industry-standard DFT and ATPG tools such as Synopsys DFT Compiler, TetraMAX, or Cadence Modus
• Experience in MBIST/LBIST insertion and validation
• Familiarity with JTAG/IEEE 1149.x standards and boundary scan implementation
• Good knowledge of Verilog/SystemVerilog and scripting languages like Tcl or Python
• Understanding of physical design impact on DFT (timing, congestion, power)
• Strong debugging and problem-solving skills
• Desired Skills:
• Experience with low-power DFT techniques and multi-voltage domain designs
• Exposure to silicon bring-up and yield analysis
• Knowledge of tester platforms like Advantest or Teradyne
• Experience working in advanced nodes (7nm/5nm or below)
• Strong communication and collaboration skills
• Ability to work in cross-functional global teams
• Self-driven with a proactive approach to problem-solving

Compensation can differ depending on factors including but not limited to the specific office location, role, skill set, education, and level of experience. UST provides a reasonable range of compensation for roles that may be hired in various U.S. markets as set forth below.

Role Location: California

Compensation Range: $65,000-$98,000

Benefits

Full-time, regular employees accrue a minimum of 10 days of paid vacation per year, receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year), 10 paid holidays, and are eligible for paid bereavement leave and jury duty. They are eligible to participate in the Company's 401(k) Retirement Plan with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance, as well as the following Company-paid Employee Only benefits: basic life insurance, accidental death and disability insurance, and short- and long-term disability benefits. Regular employees may purchase additional voluntary short-term disability benefits, and participate in a Health Savings Account (HSA) as well as a Flexible Spending Account (FSA) for healthcare, dependent child care, and/or commuting expenses as allowable under IRS guidelines. Benefits offerings vary in Puerto Rico.

Part-time employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year) and are eligible to participate in the Company's 401(k) Retirement Plan with employer matching.

Full-time temporary employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year) and are eligible to participate in the Company's 401(k) program with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance.

Part-time temporary employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year).

All US employees who work in a state or locality with more generous paid sick leave benefits than specified here will receive the benefit of those sick leave laws.