Texas Instruments

DFM RET Engineer

Texas Instruments$100K — $130K *
Technical Services
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • Master's or Ph.D. in Electrical Engineering, Physics, Materials Science, or related field
  • 5+ years of hands-on OPC and DFM experience in the semiconductor industry
  • Strong understanding of optical lithography principles and RET
  • Hands-on experience with industry-standard OPC tools
  • Familiarity with 28nm/22nm process constraints and lithographic limitations
  • Proficiency in scripting languages such as Python or TCL

Responsibilities

  • Develop, evaluate, and implement advanced OPC models for 28nm technologies
  • Perform comprehensive DFM analysis on product designs
  • Collaborate with design teams to define DFM guidelines
  • Work with lithography teams to optimize OPC recipes
  • Interface with engineers to co-optimize layout structures
  • Analyze lithography process data to identify defects
  • Evaluate and qualify new OPC/DFM software tools
  • Develop and maintain automation scripts for OPC/DFM flows
  • Contribute to DFM-aware layout methodologies

Benefits

  • Access to cutting-edge technology and innovative projects
  • Opportunities for career advancement within a global leader
  • Supportive company culture emphasizing teamwork and collaboration
  • Access to professional development and mentoring programs
Full Job Description
Job Description

Job Description:

At 28nm and below, photolithography cannot simply print a chip design as drawn but rather optical diffraction causes critical features to print incorrectly, with direct consequences to yield and device performance. Solving that problem is your job. As a DFM/OPC Engineer in TI's Resolution Enhancement Techniques (RET) team within ATD, you are the technical authority responsible for bridging the gap between what designers draw and what the fab can reliably print. You'll develop, optimize, and deploy Optical Proximity Correction (OPC) models and Design for Manufacturability (DFM) solutions that ensure every product tapeout can be accurately realized in silicon at 28nm at yield entitlement. This role sits at the intersection of computational lithography, layout design, and process integration; your work is a prerequisite for every analog product TI ships from LFAB.

Responsibilities:
  • Develop, evaluate, and implement advanced OPC models and recipes for 28nm and equivalent advanced node technologies
  • Perform comprehensive DFM analysis on product designs, identifying and mitigating potential manufacturing issues (e.g., hotspots, yield detractors)
  • Collaborate with design teams to define DFM guidelines and ensure layout compliance with manufacturing capabilities
  • Work with lithography and process engineering teams to optimize OPC recipes and improve patterning performance, yield, and process window
  • Interface with OPC and lithography engineers to co-optimize layout structures for printability
  • Analyze lithography process data and wafer yield data to identify root causes of patterning defects and drive corrective actions
  • Evaluate and qualify new OPC/DFM software tools and methodologies
  • Develop and maintain automation scripts for OPC/DFM flows
  • Contribute to DFM-aware layout methodologies for custom analog IPs
  • Mentor junior engineers and contribute to team knowledge sharing


Qualifications

Minimum Requirements:
  • Master's or Ph.D. in Electrical Engineering, Physics, Materials Science, or related field
  • 5+ years of hands-on OPC and DFM experience in the semiconductor industry
  • Strong understanding of optical lithography principles and RET (OPC, SRA, assist features, mask technology)
  • Hands-on experience with industry-standard OPC tools (e.g., Synopsys Sentaurus Lithography, Siemens EDA Calibre, ASML Brion)
  • Familiarity with 28nm/22nm process constraints and lithographic limitations
  • Proficiency in scripting languages (Python, TCL, Perl, or equivalent)


Preferred Qualifications:
  • Experience with analog layout interaction with lithography and OPC flows
  • Familiarity with layout tools (e.g., Cadence Virtuoso); knowledge of DRC and LVS
  • Experience applying machine learning or AI techniques to OPC/DFM problems
  • Strong cross-functional collaboration and analytical skills


About the Team

TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.

About Texas Instruments

National Semiconductor is a semiconductor manufacturer, specializing in analog devices and subsystems, headquartered in Santa Clara, California. The products of National Semiconductor include power management circuits, display drivers, audio and operational amplifiers, communication interface products and data conversion solutions. National's key markets include wireless handsets, displays and a variety of broad electronics markets, including medical, automotive, industrial, and test and measurement applications.

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Industry
Net Income
$5.5 billion
Founded
1930
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Revenue
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