The Role

SiFive is looking for a Design Verification Engineer II to drive verification of CPU subsystem functionality in high-performance core development.

This is a Engineer II individual-contributor role for an engineer who can independently own complex verification problems, define strategy for their subsystem, and raise methodology quality across the broader CPU DV effort.

The role is suited for engineers working on one or more CPU subsystem areas such as Frontend, Midcore, Load-Store Unit, memory ordering and consistency, hardware prefetch, or related microarchitectural interactions. You will work closely with architecture, RTL, performance, compiler, system verification, and software teams to ensure design intent is captured correctly, risks are identified early, and signoff quality is achieved.

Responsibilities

• Own verification planning and execution for one or more CPU subsystem areas, from block-level verification through subsystem integration and signoff.
• Review specifications and microarchitecture from a verification perspective, identify ambiguity early, and influence design quality and debuggability.
• Develop and maintain scalable verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for complex CPU subsystem behavior.
• Define and execute directed and constrained-random test scenarios that expose corner cases in pipeline interactions, load/store ordering, hazard handling, memory consistency, and related subsystem behavior.
• Drive failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.
• Write functional coverage, analyze code and functional coverage, and close coverage holes to ensure verification completeness and signoff quality.
• Contribute reusable verification methodology, automation, and infrastructure improvements that increase quality and productivity across future CPU generations.
• Partner effectively across design, architecture, compiler, performance, and system teams to close verification gaps from multiple perspectives.

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• Strong hands-on experience with SystemVerilog and UVM-based verification.
• Direct experience with CPU/core verification and solid understanding of computer architecture and CPU microarchitecture.
• Experience in one or more CPU subsystem areas such as Frontend, Midcore, Load-Store Unit, memory ordering and consistency, or hardware prefetch verification.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and closure.
• Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution.

Preferred Qualifications

• Experience with out-of-order core verification.
• Experience using formal verification, emulation, or performance-oriented verification for high-risk or performance-sensitive problems.
• Experience mentoring engineers and influencing verification methodology beyond the immediate block or feature area.
• Familiarity with Python, C/C++, or other scripting/programming languages used for DV infrastructure and automation.
• Strong interpersonal skills and the ability to influence people across disciplines.

What Success Looks Like

• Verification plans capture real architectural and microarchitectural risks early and completely.
• Difficult CPU subsystem bugs are found early, debugged efficiently, and closed with durable solutions.
• Coverage quality, testbench quality, and subsystem signoff readiness improve meaningfully under your ownership.
• Architecture, design, and DV teams rely on you as a strong technical partner for difficult CPU verification challenges.

You will be part of a high performance Out-of-Order Core team that focuses on verification of components such as Frontend, Mid-Core, Load-Store Unit, Integer and Floating Execution Unit, as well as Vector Unit that implement the latest RVV.

BS/MS Degree in EE, CE or CS

5-8 years relevant experience with IP/Component functional verification, preferably in Core/CPU verification

Deep understand of computer architecture is desired

Experienced developer using Object Oriented Programing principles

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! 

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.