Google

Design Verification Engineer

Google$163K — $237K *
Technical Services
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; equivalent practical experience considered.
  • 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
  • Experience developing and maintaining verification test benches, test cases, and test environments.
  • Master's degree or PhD preferred with a focus on computer architecture.
  • Expertise in low-power design verification and various verification techniques.

Responsibilities

  • Plan verification of digital design blocks by analyzing specifications and collaborating with design engineers.
  • Create and enhance verification environments using SystemVerilog and UVM; leverage SVA and formal tools for verification.
  • Debug tests in collaboration with design engineers to ensure successful delivery of design blocks.
  • Measure verification coverage to identify gaps and track progress toward tape-out.
  • Identify and document coverage measures for different stimuli and edge cases.

Benefits

  • Comprehensive health, dental, and vision coverage.
  • 401(k) plan with company match.
  • Generous paid time off and sick leave policies.
  • Opportunities for professional development and continuous learning.
  • Participation in employee stock plans.
Full Job Description
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
  • Experience developing and maintaining verification test benches, test cases, and test environments.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience in low-power design verification.
  • Experience with different verification techniques and methodologies including formal, GLS, UPF based Power simulations, UVM and C based testing, etc. to achieve bug-free Silicon in complex SoCs.
  • Experience in ARM and RISC-V processor based DV including tool chains and C based testing.


Responsibilities
  • Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or verify designs with SystemVerilog Assertions (SVA) and formal tools.
  • Debug tests with design engineers to deliver design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.
  • Identify and write all types of coverage measures for stimulus and corner-cases.


US: $163000 - $237000 (USD) 15% bonus target bonus equity benefits

Learn more about benefits at Google .

About Google

Google is a multinational technology company that specializes in Internet-related services and products. These include online advertising technologies, search engine, cloud computing, software, and hardware. Google was founded in 1998 by Larry Page and Sergey Brin while they were Ph.D. students at Stanford University. The company has grown tremendously since then and has become one of the most valuable companies in the world. Google's mission is to organize the world's information and make it universally accessible and useful.
Learn more about Google
Size
156,500 employees
Market Cap
$1,115.4 billion
Industry
Net Income
$40.2 billion
Founded
1998
5 Year Trend
+23.3%
Revenue
$182.5 billion
NASDAQ

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