Design Verification Engineer

Cerebras Systems

$190K — $230K *
Information Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Great debugging and problem-solving skills.
  • Deep knowledge of SystemVerilog testbench, DPI and UVM.
  • Excellent programming skills in object-oriented design practices.
  • Experience developing scalable and portable testbenches and components.
  • Knowledge of verification methodologies and tools including simulators and waveform viewers.
  • Proficient in scripting languages like Python or Perl.
  • Good interpersonal skills with the ability to collaborate effectively.
  • Self-motivated and eager to solve complex problems.
  • 3+ years of hands-on Design Verification experience.

Responsibilities

  • Collaborate with architects, designers, and engineers to validate design quality for silicon.
  • Develop and implement comprehensive verification strategies based on micro-architecture.
  • Create reusable verification environments that include stimulus, checkers, and coverage components.
  • Execute tests, manage regressions, and debug any test failures encountered.
  • Work with cross-functional teams including design, firmware, and validation departments.
  • Analyze and debug complex issues throughout simulation, emulation, and silicon bring-up stages.
  • Enhance verification infrastructure and workflows to improve overall efficiency and quality.
  • Contribute to evolving verification methodologies and best practices organization-wide.

Benefits

  • Collaborative work environment with cross-functional teams.
  • Opportunities for professional development and skills enhancement.
  • Access to innovative technology and methodologies.
  • Potential involvement in cutting-edge design verification strategies.
Full Job Description
Key Responsibilities
  • Work with architects, designers, post silicon and software engineers to ensure a high-quality design that works for silicon.
  • Develop and implement verification strategies, detailed tests and coverage plans based on micro-architecture.
  • Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage.
  • Implement tests, manage regressions, gather coverage, and debug test failures.
  • Collaborate with cross-functional teams including architecture, RTL design, physical design, firmware, and validation.
  • Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases.
  • Continuously enhances verification infrastructure and flows to improve efficiency and quality.
  • Contribute to the evolution of the overall verification methodology and best practices across the organization.
Skills and Qualifications
  • Great debugging and problem-solving skills.
  • Deep knowledge of SystemVerilog testbench, DPI and UVM.
  • Excellent programming skills and knowledge of software engineering practices including object-oriented design.
  • Experience developing scalable and portable testbenches and components.
  • Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, and gate level simulations.
  • Proficient in scripting languages such as Python or Perl.
  • Good interpersonal skills and the ability to work as a standout colleague are a must.
  • Extremely self-motivated and eager to solve problems
  • 3+ years of Design Verification experience.
Desired Skills and Qualifications
  • Knowledge of pipelined processor architecture.
  • BS or MS in Computer Science or Electrical Engineering.
  • 3+ years of hands-on Design Verification experience.

Location: Sunnyvale, CA

The base salary range for this position is $190,000 to $230,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

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