THE ROLE: 

AMD is seeking an experienced Design Verification Engineer to join our team developing next-generation high-performance computing and semiconductor products. In this role, you will be responsible for verifying complex PCI Express (PCIe) IP and subsystem designs using industry-leading verification methodologies, including SystemVerilog and UVM. You will collaborate closely with architecture, design, and validation teams to develop comprehensive verification strategies, drive coverage closure, and ensure first-pass silicon success.

This position provides broad exposure to the ASIC development lifecycle, from architectural definition and RTL development through verification signoff and silicon bring-up. The ideal candidate is passionate about solving challenging technical problems, improving verification efficiency, and delivering high-quality designs in a fast-paced, collaborative environment.

THE PERSON:

• Strong experience with SystemVerilog and UVM-based verification methodologies.
• Experience developing verification environments, testbench architectures, and reusable verification components.
• Knowledge of RTL design concepts and Verilog HDL.
• Experience with ASIC or SoC verification flows.
• Programming experience with C/C++, Java, or other object-oriented languages.
• Scripting experience using Perl, Python, Ruby, Shell, or similar languages in Linux/UNIX environments.
• Experience with industry-standard simulators and debug tools such as VCS, Xcelium/NCSIM, Questa, and Verdi.
• Knowledge of PCI Express (PCIe) architecture and protocols.
• Understanding of processor and system architectures, including x86 and ARM.
• Experience with on-chip interconnects and industry-standard interfaces such as AXI and PIPE.

KEY RESPONSIBILITIES:

• Develop, review, and execute comprehensive verification plans to ensure feature and functional coverage.
• Design and implement scalable verification environments using SystemVerilog and UVM.
• Develop reusable verification components, including UVCs, BFMs, models, monitors, and checkers.
• Create, maintain, and execute constrained-random and directed test suites.
• Analyze functional, code, and assertion coverage metrics and drive coverage closure.
• Develop assertions, scoreboards, and other verification infrastructure to improve design quality.
• Debug simulation failures and regression issues to identify root causes and drive resolution.
• Reproduce and analyze silicon-reported functional issues within simulation environments.
• Leverage internal and third-party EDA/CAD tools to support verification development and execution.
• Participate in code reviews and verification signoff activities.
• Collaborate with design, architecture, and validation teams throughout the product development cycle.
• Provide technical leadership by driving verification projects from planning through signoff.

PREFERRED EXPERIENCE:

• Strong experience with SystemVerilog and UVM-based verification methodologies.
• Experience developing verification environments, testbench architectures, and reusable verification components.
• Knowledge of RTL design concepts and Verilog HDL.
• Experience with ASIC or SoC verification flows.
• Programming experience with C/C++, Java, or other object-oriented languages.
• Scripting experience using Perl, Python, Ruby, Shell, or similar languages in Linux/UNIX environments.
• Experience with industry-standard simulators and debug tools such as VCS, Xcelium/NCSIM, Questa, and Verdi.
• Knowledge of PCI Express (PCIe) architecture and protocols.
• Understanding of processor and system architectures, including x86 and ARM.
• Experience with on-chip interconnects and industry-standard interfaces such as AXI and PIPE.

ACADEMIC CREDENTIALS:

• Masters or bachelor in electrical or computer engineering

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Benefits offered are described:  AMD benefits at a glance.