Qualifications

• Master's degree in Computer Engineering, Electrical Engineering, or a related field.
• Experience in design verification, including drafting detailed verification documentation and developing test cases.
• Understanding of functional verification fundamentals, environment planning, and test plan generation.
• Proficiency in Universal Verification Methodology (UVM) based environment development.
• Knowledge of System Verilog Assertions (SVA) for protocol checker development.
• Experience with Advanced Microcontroller Bus Architecture (AMBA) Protocol for system-on-chip designs.
• Familiarity with leveraging AI and Machine Learning for verification processes.

Responsibilities

• Research, design, develop, and test electronic components and systems for EDA and semiconductor IP.
• Serve as a Functional Verification Engineer for DDR Memory Controller and Phy IP development.
• Perform functional verification for Cadence's DDR Memory Controller and Phy IP solutions.
• Enhance existing functional verification environments by adding new features.
• Ensure customer configurations are validated during verification regressions and assist customers in resolving issues.
• Verify designs to meet technical and quality standards, focusing on functional and code coverage.
• Work with a hybrid model allowing some telecommuting.

Benefits

• Work from home opportunities available.
• Engage in cutting-edge technology development in EDA and semiconductor fields.