This role specifically requires a skilled ASIC Verification Engineer with expertise in cache coherency protocols and AMBA-based interconnects (AXI, ACE, CHI). You will play a key role in verifying the cache protocol compliance and ensuring coherency across CPU and GPU memory subsystems, ensuring that coherency is maintained across complex memory hierarchies in high-performance ASIC designs. This position demands a motivated individual who understands how complex SOCs, and IPs are built, has intimate knowledge of client requirements, and comprehends various development cycles. It requires deep knowledge of System Verilog, UVM, and C++, along with a solid grasp of ASIC verification methodologies.
What you'll be doing: - Responsible for ASIC design verification for various processing blocks within a SOC, with a strong focus on cache coherency protocols and complex memory hierarchies.
- Develop and complete test plans for cache coherency verification of ASIC-based SoCs using UVM-based environments.
- Design and implement constrained-random and directed System Verilog testbenches targeting multi-level cache hierarchies and interconnect fabric.
- Collaborate extensively with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams to ensure comprehensive first-time right verification plans and execution.
- Drive the development of silicon and platform verification strategies and methodologies.
What we need to see: - B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience).
- 5+ years of experience in ASIC verification, particularly in cache coherency or memory subsystem verification.
- Strong knowledge of System Verilog and UVM methodology.
- Hands-on experience with AMBA protocols, especially AXI, ACE, and CHI, demonstrating a strong background with AMBA protocols such as AXI, CHI, ATB, etc.
- Familiarity with SoC architectures, memory models, and CPU-cache interactions.
- Proficiency in scripting languages (Python, Perl, TCL) and working knowledge of C/C++ for testbench or model integration.
Ways to stand out from the crowd:- Experience with formal verification or assertion-based verification (SVA).
- Knowledge of RISC-V or ARM architecture and system-level cache subsystems.
- Exposure to coherency modeling tools, verification IPs, or emulation platforms (e.g., Palladium, Veloce).
- Experience in GPU-based verification is desirable.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until August 8, 2026.
This posting is for an existing vacancy.
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