THE ROLE:

The Full Custom IC Layout team is seeking an engineer to design and implement layouts for digital and analog circuits based on schematics using industry-standard CAD tools and advanced semiconductor process technologies. Examples of layouts developed by our team include high-speed I/O drivers and receivers, delay lines, duty-cycle correction (DCC) circuits, calibration circuits, clock buffers, and custom digital circuits.

This team plays a critical role in enabling AMD's next-generation semiconductor products. Team members collaborate across multiple engineering disciplines to solve complex technical challenges and contribute to innovative solutions used by customers worldwide. In this role, you will have the opportunity to work on impactful technologies while developing expertise in advanced process nodes, custom layout methodologies, and physical design verification.

THE PERSON:

In this role, you will contribute across multiple phases of the design lifecycle, from initial floor planning and routing of lower-level logic gates through top-level integration, verification, and tape out activities. Day-to-day responsibilities include creating lower-level cell layouts and assembling them into larger IP blocks. You will use a variety of verification tools throughout the design hierarchy, including DRC, LVS, EM/IR, ERC, and Latch-up/ESD verification. As you grow in the role, you may also collaborate with and help coordinate work across globally distributed engineering teams and external design partners.

KEY RESPONSIBILITIES:

• Create high-quality, manufacturable layouts for digital and analog building blocks at the transistor level using Cadence Virtuoso.
• Floorplan, route, and assemble lower-level cells into macros.
• Build black-box and abstract models consumed by other teams and contribute to tape out collateral for custom blocks.
• Run hierarchical verification at the cell and macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and drive issue resolution in collaboration with circuit designers.
• Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality.

PREFERRED EXPERIENCE:

• Experience in custom IC layout design is preferred. Candidates with relevant industry, research, internship, or project experience are encouraged to apply.
• Demonstrated understanding of CMOS device and circuit theory, as well as analog and digital layout best practices.
• Experience using industry-standard layout tools such as Cadence Virtuoso and Calibre.
• Experience with LVS, DRC, EMIR, and other physical verification methodologies.
• Exposure to advanced process nodes (e.g., 2nm, 3nm, 5nm, or 7nm technologies).
• Experience with IP or standard-cell layout, high-speed differential signaling, PLL/DLL/VCO circuits, DACs, power pads, and in-context XOR verification.
• Experience with scripting or automation using Perl, TCL, SVRF/TVF, SKILL, or similar languages is a plus.

ACADEMIC CREDENTIALS:

• Bachelor’s or master’s degree in Electrical Engineering, Mechanical Engineering, Electronics, or a related technical field.

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Benefits offered are described:  AMD benefits at a glance.

This posting is for an existing vacancy.