Job Area:Engineering Group, Engineering Group > CPU Engineering
General Summary:Qualcomm Data Center team is developing High performance, Energy efficient server solution for data center applications. We are looking for highly talented, innovative, teamwork-oriented individuals for our cutting-edge technology work!
As a CPU Floorplan and Integration Engineer, you will work with microarchitecture, RTL design and physical design teams to design, floorplan and integrate the CPU designs meeting aggressive power, area and performance goals using industry standard tools/flows.
Ideal candidates should have
- Proficiency in synthesis, place and route, and signoff timing/power analysis.
- Expertise in block-level implementation as well as full chip floorplanning and power grid planning.
- Skilled in physical design, integration, and verification of large processor and system-on-chip (SoC) designs.
- Extensive knowledge of low power and high-performance design methodologies.
- Strong understanding of circuit and layout design principles.
- Proven ability to work effectively within a team environment.
- In-depth understanding of extraction, static timing analysis (STA), and electromigration and IR drop (EMIR) flows and methodologies.
Minimum Qualifications:• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Preferred qualifications
- Experience in deep submicron process technology nodes is strongly preferred.
- Experience as a key technical lead driving development and delivery of physical design databases is a plus
- Solid understanding industry standard tools for synthesis, place & route and tapeout flows.
Roles and Responsibilities
- Ensure the designs are validated for functional and electrical robustness.
- Perform CPU physical design tasks, including floorplanning, Bump/RDL planning, IP integration, power/ground generation, and pin assignment.
- Oversee full chip floorplan, area optimizations, block partitioning, and pin assignments.
- Manage chip-level place and route, and finalize the CPU database for construction and verification.
- Coordinate custom layout integration.
- Collaborate with external teams to fulfill IP technical and delivery requirements.
- Develop workflows for chip integration and analysis.
Pay range and Other Compensation & Benefits: $142,200.00 - $213,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
