The Role and Impact:As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL) code and simulation for the CPU, enabling creation of cell libraries, functional units, and CPU IP blocks for integration into full-chip designs. Your expertise will be pivotal in defining architecture and microarchitecture features, ensuring Intel continues to deliver innovative solutions that lead the industry in performance, energy efficiency, and design integrity. By contributing to the development and optimization of logic structures, you will help create technology that enriches the lives of every person on Earth, while enabling Intel to achieve its broader mission of engineering a brighter future.
Key Responsibilities:- Develop and optimize logic design, register transfer level (RTL) coding, and simulation for the CPU.
- Participate in defining the architecture and microarchitecture features of the CPU design.
- Write RTL and optimize logic for power, performance, area, and timing goals.
- Ensure design integrity for physical implementation through effective strategies, tools, and methods.
- Review verification plans to ensure design features are correctly validated and resolve failing RTL tests.
- Document microarchitectural specifications (MAS) for the CPU features.
- Collaborate with SoC customers to ensure seamless integration and high-quality performance of the CPU block.
Qualifications:You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum Qualifications:Bachelor's degree in electrical engineering, computer engineering, or computer science with 7+ years of relevant experience; OR Master's degree with 5+ years of experience; OR PhD with 2+ years of experience.
- 7+ years experience in RTL design using Verilog, V2K, or System Verilog, with strong knowledge of hardware modeling and logic debug environments.
- 5+ years experience with modern energy-efficient and low-power logic design methods, including techniques applicable to high-frequency optimization.
- 5+ years experience in Cross-clock domain crossings and power aware design.
- 3+ years experience in scripting languages such as TCL, Perl, or Python.
Preferred Qualifications:- Knowledge on CPU power-management namely power/electrical budgeting, dynamic voltage and frequency scaling, thermal, P/C states and reset sequence handling.
- Comprehensive knowledge of Intel Architecture ISA and system architecture, including x86 assembly language.
- Experience with high-speed circuit design and optimization, specifically for datapath, circuits, and arrays.
- Familiarity with circuit planning and timing convergence processes.
- Ability to leverage broad understanding of CPU architecture to deliver impactful solutions.
- Proficient with static timing analysis, UPF and lint checks.
- Good communication skills.
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location:US, Texas, Austin
Additional Locations:US, Arizona, Phoenix
Business group:Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
