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X In most instances, this position requires in-person interviews as part of the hiring process.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
Austin, TX, USA; Mountain View, CA, USA.
Minimum qualifications: - Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
- 8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows.
- Experience developing, deploying, and supporting DFT flows ( ATPG, Logic Vision, BIST, or JTAG).
Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
- Experience applying AI/ML-assisted DFT design techniques for scaling and physical design closure.
- Experience with scripting in Python, Tcl, or Perl, and data mining for QoR metrics.
- Experience developing novel DFT solutions, silicon bring-up, and validation.
- Knowledge of high-performance, low-power design DFT techniques and end-to-end silicon flows.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $236000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Partner with cross-functional teams to architect, implement, and verify design-for-test (DFT) solutions for advanced CPU designs.
- Pioneer custom DFT methodologies using industry-standard EDA tools to accelerate turnaround times and test coverage.
- Develop, debug, and optimize production test patterns for automatic test equipment flows to support silicon delivery.
- Mentor peers and foster cross-functional engineering collaboration across the DFT organization.
