Job Details:Job Description:Position OverviewAs a Collateral Device Engineer, you will be responsible for developing device collateral including test chip designs, DTCO, product scribe line layouts, managing OPC/Mask requests, and overseeing design rules and waivers for technologies currently in large-volume manufacturing. This role focuses on general-purpose logic CMOS technologies to support a broad spectrum of products and markets, including:
- High-Performance Compute
- Mobile
- Mixed Signal
- Memory Controllers
- Diverse emerging applications
Key Responsibilities - Design and develop comprehensive device collateral including test chip architectures and product scribe line layouts to support technology characterization and monitoring
- Collaborate with Technology Development teams to establish and refine design rules for newly developed device architectures and customize collateral to meet customer-specific requirements
- Develop and manage design-rule waiver processes, ensuring proper documentation and risk assessment for customer applications
- Create and optimize scribe line monitoring structures for yield enhancement and process control in high-volume manufacturing
- Work with manufacturing teams to implement device collateral that meets specifications, yield targets, and provides robust process monitoring capabilities
- Drive the development of standardized test chip methodologies and scribe line layouts compatible with Intel's existing manufacturing processes and platforms
- Analyze device parametric data from test chips and scribe line structures to drive continuous improvement in device performance and manufacturability
- Provide technical guidance on design rule compliance and waiver justifications to cross-functional teams and customers
- Stay current with industry trends in device collateral design, test methodologies, and design rule evolution to inform development strategies
Qualifications:Minimum Qualifications- Master's degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering with a focus on test chip design and device collateral development
Experience in the following:
- CMOS semiconductor device physics and test chip design for advanced transistor device architecture
- Scribe line layout design and process monitoring structure development
- Design rule development, validation, and waiver management processes
- DTCO skills, including SRAM, Standard Cells, and ability to serve as the key interface and bridge between Process Integration, Yield, Device, and Design teams
Preferred Qualifications- Ph.D. in Electrical Engineering, Physics, or related field with 5+ years of experience in CMOS device engineering and collateral development
- Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub-3nm GAA FETs
Experience in the following:
- Design Rule Checker (DRC) development and physical verification flows
- Experience in a High-Volume Manufacturing environment with a focus on yield monitoring and process control structures
- Statistical Process Control (SPC) and advanced data analytics for device collateral optimization
- Mask generation including Boolean/OPC
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location:US, California, Santa Clara
Additional Locations:US, Arizona, Phoenix, US, Oregon, Hillsboro
BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $161,550.00-317,600.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
