Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:Job Description
The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. The responsibility of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology. Involve in developing automation to improve verification efficiency.
Qualifications- Bachelor's degree in Engineering, Science, or a closely related field
- 2+ years of experience with ASIC design and verification tools, techniques, and methodology
Preferred Qualifications- Master's degree in Computer Science, Electrical Engineer, Computer Engineering, or a closely related field
- 6+ years of experience with ASIC design and verification tools, techniques, and methodology
- 6+ years of experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL.
- 6+ years of experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills.
- 6+ years of experience with developing block-level testbench environment using SystemVerilog
- 6+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification
- 6+ years of experience with scripting/automation skills using either Perl or python
- Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable (not mandatory)
- Knowledge or experience with Assertion Based Formal Verification is desirable (not mandatory)
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
Pay range and Other Compensation & Benefits: $115,600.00 - $173,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
