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X Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
San Diego, CA, USA; Mountain View, CA, USA.
Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with ASIC power management architecture.
- Experience with hardware or software power control flows and methodology.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
- Experience with power components, power modeling, and power management techniques such as Voltage Frequency Scaling (DVFS/AVS), etc.
- Experience modeling and validating in virtual prototyping and TLM environments.
- Experience with algorithmic development and prototyping software for power management.
- Knowledge of the impact of software and architectural design decisions on power and thermal behavior of the system, such as thermal mitigation and scheduling, and cross-layer policy design.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The US base salary range for this full-time position is $163,000-$237,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities - Drive architectural analysis for mempath traffic patterns, from collecting silicon traffic patterns for key tensor CUJs, to mapping them to pre-silicon CUJ estimates and closing correlation gaps.
- Oversee end-to-end correlation from pre-silicon micro benchmark power estimates to CUJ modeling estimates, with a focus on architectural assumptions used for modeling.
- Propose architectural features/requirements for mempath to improve overall Key Performance Indicators (KPIs).
- Perform algorithm development, modeling, and analysis of various architecture approaches.
