Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with formal and design verification.
- Experience with SystemVerilog or Verilog.
- Experience working with one or more formal verification tools (e.g., Jasper, VC Formal, Questa Formal, 360-DV).
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
- 6 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based Integrated Circuits (ICs) and chips.
- Experience with scripting languages.
- Excellent communication and collaboration skills.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Formal Verification Engineer, you will contribute formal verification expertise to verify the digital designs, with a specific focus on TPU architecture and its integration within AI/ML- driven systems. You will be part of a team developing ASICs used to accelerate computation in data centers. You will have responsibilities in areas such as project definition, formal verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
US: $138000 - $197000 (USD) 15% bonus target equity benefits
Responsibilities- Plan the formal verification strategy, create the properties and constraints for the digital design blocks.
- Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
- Resolve difficult to verify properties.
- Contribute improvements to methodologies to enhance formal verification results.
- Architect and implement reusable formal verification components.
