Renesas Electronics America

ASIC Digital Verification Engineer

Renesas Electronics America$76K — $100K *
Information Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's degree with up to 2 years of relevant experience or recent master's grad without experience.
  • Familiarity with functional specifications and the ability to create detailed verification plans.
  • Proficient in SystemVerilog and UVM environments for digital verification.
  • Experience with Synopsys or Cadence simulation tools.
  • Knowledge of SystemVerilog assertions, functional coverage, and code coverage.
  • Demonstrated ability to learn quickly and work independently.
  • Strong team collaboration and communication skills.
  • Ability to operate in a Unix/Linux environment.

Responsibilities

  • Define and implement self-checking test cases based on functional requirements.
  • Contribute to the development of verification infrastructure components.
  • Triage regressions and debug RTL and gate-level simulations.
  • Analyze coverage and collaborate with teams to resolve verification issues.
  • Engage with local and remote design and verification team members.

Benefits

  • 100% onsite work environment to foster team collaboration and engagement.
  • Opportunities for professional growth and contribution to cutting-edge technology development.
Full Job Description
ENTRY LEVEL - Bachelor's degree with up to 2 years of experience or a recent master's grad with no experience.

100% onsite

Our Ottawa office is looking for a talented ASIC Digital Verification Engineer to join our team. Our team is developing industry-leading mixed-signal Digital PLL Application specific integrated circuits. You can be a part of a growing mixed design and verification team giving you a chance to make a significant impact. You would not only be contributing to the actual testcase development but also be part of the verification planning and the continuous improvement of our verification environment using the latest methodologies.

Responsibilities
  • Define and implement self-checking test cases based on functional requirements
  • Contribute to our ever-evolving verification infrastructure components
  • Triage of regressions, debug of RTL and Gate level simulations, analysis of coverage, and working with other teams to resolve issues and achieve verification closure
  • Work with diverse design and verification team members, local and remote


Qualifications
  • ENTRY LEVEL - Bachelor's degree with up to 2 years of experience or a recent master's grad with no experience.
  • Understanding standard specifications/ functional specifications/ feature enhancements for the product to create and execute detailed verification plans
  • Knowledge of SystemVerilog and UVM environments for digital verification
  • Experience with Synopsys and/or Cadence simulation tools
  • Experience with System Verilog assertions, functional coverage, and code coverage
  • Fast learner with the ability to work under minimal supervision
  • Effective team player with good communication skills
  • Ability to work in a Unix/Linux operating system environment


Additional Information

This posting is for a replacement vacancy. The expected annual pay range for this position is $76,000 - $100,000. This position is also eligible for bonus opportunities and commission pay. Please note that the final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate.

Videos To Watch
https://www.youtube.com/embed/k-zs4tB6nNc

About Renesas Electronics America

Renesas Electronics America is a leading supplier of advanced semiconductor solutions including microcontrollers, SoC solutions and a broad range of analog and power devices, with operations spanning research, development, design and manufacturing for a wide range of applications.
Learn more about Renesas Electronics America
Size
2,000 employees
Industry

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